Power system applications of fiber optic sensors

This document is a progress report of work done in 1985 on the Communications and Control for Electric Power Systems Project at the Jet Propulsion Laboratory. These topics are covered: Electric Field Measurement, Fiber Optic Temperature Sensing, and Optical Power transfer. Work was done on the measurement of ac and dc electric fields. A prototype sensor for measuring alternating fields was made using a very simple electroscope approach. An electronic field mill sensor for dc fields was made using a fiber optic readout, so that the entire probe could be operated isolated from ground. There are several instances in which more precise knowledge of the temperature of electrical power apparatus would be useful. This report describes a number of methods whereby the distributed temperature profile can be obtained using a fiber optic sensor. The ability to energize electronics by means of an optical fiber has the advantage that electrical isolation is maintained at low cost. In order to accomplish this, it is necessary to convert the light energy into electrical form by means of photovoltaic cells. JPL has developed an array of PV cells in gallium arsenide specifically for this purpose. This work is described

Reduction of Wind Tunnel Contamination During Flow Visualization Experiments Using Polystyrene Microspheres

Evaluation of novel methods and materials for seeding tracer particles for particle image velocimetry (PIV) was carried out in the Basic Aerodynamic Research Tunnel (BART) at NASAs Langley Research Center (LaRC). Seeding of polystyrene latex microspheres (PSLs) from ethanol/water suspensions and from the dry state was carried out using custom built seeders. PIV data generated using the novel methods were found to be in general agreement with data collected using the current seeding methods. Techniques for assessing PSL fouling of wind tunnel surfaces were identified and refined. Initial results suggest that dry seeding PSLs may allow comparable data quality to wet seeding while reducing wind tunnel screen fouling. Results also indicate that further developments to the dry seeding system should focus on increasing single particle flux into the wind tunnel. Modifications to PSLs and seeding equipment to achieve this have been identified and are discussed

Self-Aligned 3D Chip Integration Technology and Through-Silicon Serial Data Transmission

The emerging three-dimensional (3D) integration technology is expected to lead to an industry paradigm shift due to its tremendous benefits. Intense research activities are going on about technology, simulation, design, and product prototypes. This thesis work aims at fabricating through-silicon vias (TSVs) on diced processor chips, and later bonding them into a 3D-stacked chip. How to handle and process delicate processor chips with high alignment precision is a key issue. The TSV process to be developed also needs to adapt to this constraint. Four TSV processes have been studied. Among them, the ring-trench TSV process demonstrates the feasibility of fabricating TSVs with the prevailing dimensions, and the whole-through TSV process achieves the first dummy chip post-processed with TSVs in EPFL although the dimension is rather large to keep a reasonable aspect ratio (AR). Four self-alignment (SA) techniques have been investigated, among which the gravitational SA and the hydrophobic SA are found to be quite promising. Using gravitational SA, we come to the conclusion that cavities in silicon carrier wafer with a profile angle of 60° can align the chips with less than 20 µm inaccuracies. The alignment precision can be improved after adopting more advanced dicing tools instead of using the traditional dicing saws and larger cavity profile angle. Such inaccuracy will be sufficient to align the relatively large TSVs for general products such as 3D image sensors. By fabricating bottom TSVs in the carrier wafer, a 3D silicon interposer idea has been proposed to stack another chip, e.g. a processor chip, on the other side of the carrier wafer. But stacking microprocessor chips fabricated with TSVs will require higher alignment precision. A hydrophobic SA technique using the surface tension force generated by the water-to-air interfaces around the pads can greatly reduce the alignment inaccuracy to less than 1 µm. This low-cost and high throughput SA procedure is processed in air, fully-compatible with current fabrication technologies, and highly stable and repeatable. We present a theoretical meniscus model to predict SA results and to provide the design rules. This technique is quite promising for advanced 3D applications involving logic and heterogeneous stacking. As TSVs' dimensions in the chip-level 3D integration are constrained by the chip-level processes, such as bonding, the smallest TSVs might still be about 5 µm. Thus, the area occupied by the TSVs cannot be neglected. Fortunately, TSVs can withstand very high bandwidths, meaning that data can be serialized and transmitted using less numbers of TSVs. With 20 µm TSVs, the 2-Gb/s 8:1 serial link implemented saves 75% of the area of its 8-bit parallel counterpart. The quasi-serial link proposed can effectively balance the inter-layer bandwidth and the serial links' area consumption. The area model of the serial or quasi-serial links working under higher frequencies provides some guidelines to choose the proper serial link design, and it also predicts that when TSV diameter shrinks to 5 µm, it will be difficult to keep this area benefit if without some novel circuit design techniques. As the serial links can be implemented with less area, the bandwidth per unit area is increased. Two scenarios are studied, single-port memory access and multi-port memory access. The expanded inter-layer bandwidth by serialization does not improve the system performance because of the bus-bottleneck problem. In the latter scenario, the inter-layer ultra-wide bandwidth can be exploited as each memory bank can be accessed randomly through the NoC. Thus further widening the inter-layer bandwidth through serialization, the system performance will be improved

DEVELOPMENT OF A SIMPLIFIED, MASS PRODUCIBLE HYBRIDIZED AMBIENT, LOW FREQUENCY, LOW INTENSITY VIBRATION ENERGY SCAVENGER (HALF-LIVES)

Scavenging energy from environmental sources is an active area of research to enable remote sensing and microsystems applications. Furthermore, as energy demands soar, there is a significant need to explore new sources and curb waste. Vibration energy scavenging is one environmental source for remote applications and a candidate for recouping energy wasted by mechanical sources that can be harnessed to monitor and optimize operation of critical infrastructure (e.g. Smart Grid). Current vibration scavengers are limited by volume and ancillary requirements for operation such as control circuitry overhead and battery sources. This dissertation, for the first time, reports a mass producible hybrid energy scavenger system that employs both piezoelectric and electrostatic transduction on a common MEMS device. The piezoelectric component provides an inherent feedback signal and pre-charge source that enables electrostatic scavenging operation while the electrostatic device provides the proof mass that enables low frequency operation. The piezoelectric beam forms the spring of the resonant mass-spring transducer for converting vibration excitation into an AC electrical output. A serially poled, composite shim, piezoelectric bimorph produces the highest output rectified voltage of over 3.3V and power output of 145uW using ¼ g vibration acceleration at 120Hz. Considering solely the volume of the piezoelectric beam and tungsten proof mass, the volume is 0.054cm3, resulting in a power density of 2.68mW/cm3. Incorporation of a simple parallel plate structure that provides the proof mass for low frequency resonant operation in addition to cogeneration via electrostatic energy scavenging provides a 19.82 to 35.29 percent increase in voltage beyond the piezoelectric generated DC rails. This corresponds to approximately 2.1nW additional power from the electrostatic scavenger component and demonstrates the first instance of hybrid energy scavenging using both piezoelectric and synchronous electrostatic transduction. Furthermore, it provides a complete system architecture and development platform for additional enhancements that will enable in excess of 100uW additional power from the electrostatic scavenger

Heterogeneous Integration on Silicon-Interconnect Fabric using fine-pitch interconnects (≤10 �m)

Today, the ever-growing data-bandwidth demand is pushing the boundaries of the traditional printed circuit board (PCB) based integration schemes. Moreover, with the apparent saturation of semiconductor scaling, commonly called Moore's law, system scaling warrants a paradigm shift in packaging technologies, assembly techniques, and integration methodologies. In this work, a superior alternative to PCBs called the Silicon-Interconnect Fabric (Si-IF) is investigated. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform for wafer-scale systems. In this technology, unpackaged dielets are assembled on the Si-IF at small inter-dielet spacings (≤100 �m) using fine-pitch (≤10 �m) die-to-substrate interconnects. A novel assembly process using a solder-less direct metal-metal (gold-gold and copper-copper) thermal compression bonding was developed. Using this process, sub-10 �m pitch interconnects with a low specific contact resistance of ≤0.7 Ω-�m2 were successfully demonstrated. Because of the tightly packed Si-IF assembly, the communication links between the neighboring dies are short (≤500 �m) with low loss (≤2 dB), comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) at low latency (<30 ps), low energy per bit (≤0.03 pJ/b), and high data-rates (up to 10 Gbps/link), corresponding to an aggregate bandwidth up to 8 Tbps/mm. The benefits of the SuperCHIPS protocol were experimentally demonstrated to provide 5-90X higher data-bandwidth, 8-30X lower latency, and 5-40X lower energy per bit compared to existing integration schemes. This dissertation addresses the assembly technology and communication protocols of the Si-IF technology

New Trends and Applications in Femtosecond Laser Micromachining

This book contains the scientific contributions to the Special Issue entitled: "New Trends and Applications in Femtosecond Laser Micromachining". It covers an array of subjects, from the basics of femtosecond laser micromachining to specific applications in a broad spectra of fields such biology, photonics and medicine

Beamforming for 3D Transesophageal Echocardiography

In this thesis, we study beamforming techniques that offer opportunities for 3D transesophageal echocardiography imaging, especially to achieve higher frame rates. In 3D TEE with a matrix transducer, two main challenges are to connect a large number of elements to a standard ultrasound system and to achieve a high volume rate (>200 Hz). We develop a prototype miniaturized matrix transducer for pediatric patients with micro-beamforming to reduce the channel count. Initially, we propose two dual stage beamforming techniques for 1D arrays to produce high-quality images with reduced channel count: one using fixed focused receive and another with a simple summation in receive (no delays). Because of their inapplicability to the prototype transducer, we propose multiline 3D ultrasound beamforming schemes that utilize the micro-beamforming capabilities. The proposed beamforming schemes use an angle-weighted combination of the neighboring overlapping sub-volumes to suppress the crossover artifacts that are typical for parallel beamforming and produce high-quality images at a high volume rate (~300 Hz). A similar beamforming scheme adapted for a newly designed prototype matrix adult TEE probe is used for in vivo 3D imaging of the heart of a healthy adult pig to produce good quality 3D images at a high frame rate. The proposed 3D beamforming scheme can easily be adapted for matrix probes with micro-beamforming capabilities to produce good quality volume images at a high volume rate, even for a very different layout of the transmit and receive arrays

Millimeter-wave interconnects for intra- and inter-chip transmission and beam steering in NoC-based multi-chip systems

The primary objective of this work is to investigate the communication capabilities of short-range millimeter-wave (mm-wave) communication among Network-on-Chip (NoC) based multi-core processors integrated on a substrate board. To address the demand for high-performance multi-chip computing systems, the present work studies the transmission coefficients between the on-chip antennas system for both intra- and inter-chip communication. It addresses techniques for enhancing transmission by using antenna arrays for beamforming. It also explores new and creative solutions to minimize the adverse effects of silicon on electromagnetic wave propagation using artificial magnetic conductors (AMC). The following summarizes the work performed and future work. Intra- and inter-chip transmission between wireless interconnects implemented as antennas on-chip (AoC), in a wire-bonded chip package are studied 30GHz and 60 GHz. The simulations are performed in ANSYS HFSS, which is based on the finite element method (FEM), to study the transmission and to analyze the electric field distribution. Simulation results have been validated with fabricated antennas at 30 GHz arranged in different orientations on silicon dies that can communicate with inter-chip transmission coefficients ranging from -45dB to -60dB while sustaining bandwidths up to 7GHz. The fabricated antennas show a shift in the resonant frequency to 25GHz. This shift is attributed to the Ground-Signal-Ground (GSG) probes used for measurement and to the Short-Open-Load (SOLT) calibration which has anomalies at millimeter-wave frequencies. Using measurements, a large-scale log-normal channel model is derived which can be used for system-level architecture design. Further, at 60 GHz densely packed multilayer copper wires in NoCs have been modeled to study their impact on the wireless transmission between antennas for both intra- and inter-chip links and are shown to be equivalent to copper sheets. It is seen that the antenna radiation efficiency reduces in the presence of these densely packed wires placed close to the antenna elements. Using this model, the reduction of inter-chip transmission is seen to be about 20dB as compared to a system with no wires. Lastly, the transmission characteristics of the antennas resonating at 60GHz in a flip-chip packaging environment are also presented