Intrinsic variability of nanoscale CMOS technology for logic and memory.

The continuous downscaling of CMOS technology, the main engine of development of the semiconductor Industry, is limited by factors that become important for nanoscale device size, which undermine proper device operation completely offset gains from scaling. One of the main problems is device variability: nominally identical devices are different at the microscopic level due to fabrication tolerance and the intrinsic granularity of matter. For this reason, structures, devices and materials for the next technology nodes will be chosen for their robustness to process variability, in agreement with the ITRS (International Technology Roadmap for Semiconductors). Examining the dispersion of various physical and geometrical parameters and the effect these have on device performance becomes necessary. In this thesis, I focus on the study of the dispersion of the threshold voltage due to intrinsic variability in nanoscale CMOS technology for logic and for memory. In order to describe this, it is convenient to have an analytical model that allows, with the assistance of a small number of simulations, to calculate the standard deviation of the threshold voltage due to the various contributions

Design and Simulation of Short Channel Si:HfO2 Ferroelectric Field Effect Transistor (FeFET)

Non-volatile memories using ferroelectric capacitors, known as Ferroelectric Random Access Memory (FRAM) have been studied for many years, but they suffer from loss of data during read out process. Ferroelectric Field Effect Transistors (FeFETs), which are based on ferroelectric gate oxide, have been of recent interest for non-volatile memory applications. The FeFETs utilize the polarization of the ferroelectric layer incorporated into the transistor gate stack to control the channel conductivity. Therefore, in FeFET devices, the read out process is non-destructive because it is only processed by measuring the resistivity in the channel region. The drain current-gate voltage (ID-VG) characteristics of FeFETs exhibit a voltage shift due to polarization hysteresis known as the memory window , an important figure of merit of a FeFET that provides a window for the read voltage. A dielectric layer between semiconductor layer and the ferroelectric is required to reduce charge injection effect, and to compensate lattice mismatch between the ferroelectric and the semiconductor. In addition, a non-ferroelectric interfacial layer may form between the semiconductor and the ferroelectric layer. However, this dielectric layer causes a voltage drop since the system becomes equivalent to two serial capacitors. It also causes an electric field that opposes the polarization. Using a high permittivity material such as HfO2 reduces the voltage drop and the effect of depolarization. To date, the majority of the work involving FeFETs has been based on conventional ferroelectric materials such as Lead Zirconate Titanate (PZT) and Strontium Bismuth Tantalate (SBT). These materials are not compatible with standard IC processing and furthermore scaling thicknesses in PZT and SBT result in loss of polarization characteristics. Recently, ferroelectricity has been reported in doped hafnium oxide thin films with dopants such as Si, Al, and Gd. Particularly, silicon doped hafnium oxide (Si:HfO2) has shown promise. In this material, the remnant polarization considerably increases by decreasing the layer thickness. The lower permittivity of Si:HfO2 compared to that of PZT and SBT, allows to employ thinner films that reduce fringing effects. This study focuses on employing Si:HfO2 in short channel FeFETs. The study has two major objectives. First, to show that short channel FeFETs can be accomplished with large memory window. Second, to demonstrate the role of bulk layer thickness and permittivity on FeFET performance. N-channel metal oxide semiconductor FET (N-MOSFET) with printed channel length of 26 nm has been designed with Si:HfO2 as the ferroelectric layer, and TiN as the gate electrode. The effects of buffer layer thickness and permittivity and ferroelectric layer thickness on the memory window have been explored using Silvaco Atlas software that employs ferroelectric FET device physics developed by Miller et al. Polarization characteristics reported for Si:HfO2 have been incorporated in this model. The simulations performed in this study have shown that using Si:HfO2 as a ferroelectric material makes it possible to accomplish short channel FeFETs with good performance even without using buffer layers. This means it is possible to minimize depolarization effects. Using Si:HfO2 as a ferroelectric layer makes it possible to accomplish highly scaled and ultra-low-power FeFETs

Through Silicon Via Field-Effect Transistor with Hafnia-based Ferroelectrics and the Doping of Silicon by Gallium Implantation Utilizing a Focused Ion Beam System

3-dimensional integration has become a standard to further increase the transistor density and to enhance the integrated functionality in microchips. Integrated circuits are stacked on top of each other and copper-filled through-silicon VIAs (TSVs) are the industry-accepted choice for their vertical electrical connection. The aim of this work is to functionalize the TSVs by implementing vertical field-effect transistors inside the via holes. The front and back sides of 200 ... 300 µm thin silicon wafers were doped to create the source/drain regions of n- and p-FETs. The TSVFETs showed very stable saturation currents and on/off current ratios of about 10^6 (n-TSVFET) and 10^3 (p-TSVFET) for a gate voltage magnitude of 4V. The use of hafnium zirconium oxide on a thin SiO_2 interface layer as gate dielectric material in a p-TSVFET, enabled the implementation of a charge trapping memory inside the TSVs, showing a memory window of about 1V. This allows the non-volatile storage of the transistor on/off state. In addition, the demonstration of the use of gallium as the source/drain dopant in planar p-FET test structures (ion implanted from a focused ion beam tool) paves the way for maskless doping and for a process flow with a low thermal budget. It was shown, that ion implanted gallium can be activated and annealed at relatively low temperatures of 500 °C ... 700 °C.:Abstract / Kurzzusammenfassung Danksagung Index I List of Figures III List of Tables X List of Symbols XI List of Abbreviations XV 1 Introduction 1 2 Fundamentals 5 2.1 Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) 5 2.1.1 Historical Development - Technological Advancements 7 2.1.2 Field-Effect Transistors in Semiconductor Memories 10 2.2 3D Integration and the Use of TSVs (Through Silicon VIAs) 16 2.3 Doping of Silicon 19 2.3.1 Doping by Thermal Diffusion 20 2.3.2 Doping by Ion Implantation 22 3 Electrical Characterization 24 3.1 Resistivity Measurements 24 3.1.1 Resistance Determination by Four-Point Probes Measurement 24 3.1.2 Contact Resistivity 27 3.1.3 Doping Concentration 32 3.2 C-V Measurements 35 3.2.1 Fundamentals of MIS C-V Measurements 35 3.2.2 Interpretation of C-V Measurements 37 3.3 Transistor Measurements 41 3.3.1 Output Characteristics (I_D-V_D) 41 3.3.2 Transfer Characteristics (I_D-V_G) 42 4 TSV Transistor 45 4.1 Idea and Motivation 45 4.2 Design and Layout of the TSV Transistor 47 4.2.1 Design of the TSV Transistor Structures 47 4.2.2 Test Structures for Planar FETs 48 5 Variations in the Integration Scheme of the TSV Transistor 51 5.1 Doping by Diffusion from Thin Films 51 5.1.1 Determination of Doping Profiles 52 5.1.2 n- and p- TSVFETs Doped Manufactures by the Use of the Diffusion Technique 59 5.2 Ferroelectric Hafnium-Zirconium-Oxide (HZO) in the Gate Stack 81 5.2.1 Planar ferroelectric p-MOSFETs Doped by Thermal Diffusion 82 5.2.2 p-TSVFETs with Hafnium-Zirconium-Oxide Metal Gate 90 5.3 Doping by Ion Implantation of Gallium with a Focused Ion Beam (FIB) Tool 96 5.3.1 Ga doped Si Diodes 97 5.3.2 Planar p-MOSFETs Doped by Ga Implantation 108 5.3.3 Proposal for a parallel integration of Cu TSVs and p-TSVFETs 117 6 Summary and Outlook 120 Bibliography XVIII A Appendix XXXVI A.1 Resistivity and Dopant Density XXXVI A.2 Mask set for the TSVFET XXXVII A.3 Mask Design of the Planar Test Structures XXXVIII Curriculum Vitae XXXIX List of Scientific Publications XL

Doped Metal Oxide High-K Gate Dielectric for Nonvolatile Memory and Light Emitting Applications

The zirconium-doped hafnium oxide (ZrHfO) high-k thin film has excellent gate dielectric properties, such as a higher crystallization temperature, a lower defect density, and a larger effective k value. As a promising high-k material, ZrHfO has been utilized for both nonvolatile memory (NVM) and light emitting applications. Replacing the polycrystalline Si floating gate, the discrete nanocrystals embedded ZrHfO gate dielectric can achieve promising NVM performance. On the other hand, warm white light can be emitted from the thermal excitation of nano-resistors form from the dielectric breakdown of the ZrHfO Metal-Oxide-Semiconductor (MOS) capacitor. This novel solid state incandescent light emitting device (SSI-LED) unveils a new concept for the lighting device evolution. Nanocrystalline cadmium sulfide (nc-CdS) embedded ZrHfO high-k NVMs have been fabricated to reduce the frequency dispersion problem caused by defects at the nanocrystal/dielectric interface. The nc-CdS embedded device can retain about 53% of originally trapped holes for 10 years and exhibit outstanding memory function at low operation voltage. The study on the nc-CdSe embedded ZrHfO NVMs shows that the high temperature enhances the hole trapping but decreases the electron trapping. Based on the different temperature dependences, the stored electrons release faster than stored holes. The raised temperature accelerates the dielectric breakdown process by increasing defect densities and defect effective conduction radii. The post deposition annealing (PDA) atmosphere is critical to the electrical and light emission characteristics of ZrHfO SSI-LEDs. It affects the dielectric breakdown, light emission intensity and efficiency by changing compositions of the high-k stack and the nano-resistor. The electrical properties, i.e., effective resistances and Schottky barrier heights of nano-resistors have been estimated. The nano-resistor behaves neither like a conductor nor like a semiconductor. Moreover, the barrier height inhomogeneity is observed due to the random and complicated nano-resistor formation. The embedding method and the heavily doped p-Si substrate have been employed to enhance the light emission from ZrHfO SSI-LEDs. Lastly, extensive applications of this novel nano-resistor device for on-chip optical interconnects and as diode-like anti-fuses have been discussed

Doped Metal Oxide High-K Gate Dielectric for Nonvolatile Memory and Light Emitting Applications

The zirconium-doped hafnium oxide (ZrHfO) high-k thin film has excellent gate dielectric properties, such as a higher crystallization temperature, a lower defect density, and a larger effective k value. As a promising high-k material, ZrHfO has been utilized for both nonvolatile memory (NVM) and light emitting applications. Replacing the polycrystalline Si floating gate, the discrete nanocrystals embedded ZrHfO gate dielectric can achieve promising NVM performance. On the other hand, warm white light can be emitted from the thermal excitation of nano-resistors form from the dielectric breakdown of the ZrHfO Metal-Oxide-Semiconductor (MOS) capacitor. This novel solid state incandescent light emitting device (SSI-LED) unveils a new concept for the lighting device evolution. Nanocrystalline cadmium sulfide (nc-CdS) embedded ZrHfO high-k NVMs have been fabricated to reduce the frequency dispersion problem caused by defects at the nanocrystal/dielectric interface. The nc-CdS embedded device can retain about 53% of originally trapped holes for 10 years and exhibit outstanding memory function at low operation voltage. The study on the nc-CdSe embedded ZrHfO NVMs shows that the high temperature enhances the hole trapping but decreases the electron trapping. Based on the different temperature dependences, the stored electrons release faster than stored holes. The raised temperature accelerates the dielectric breakdown process by increasing defect densities and defect effective conduction radii. The post deposition annealing (PDA) atmosphere is critical to the electrical and light emission characteristics of ZrHfO SSI-LEDs. It affects the dielectric breakdown, light emission intensity and efficiency by changing compositions of the high-k stack and the nano-resistor. The electrical properties, i.e., effective resistances and Schottky barrier heights of nano-resistors have been estimated. The nano-resistor behaves neither like a conductor nor like a semiconductor. Moreover, the barrier height inhomogeneity is observed due to the random and complicated nano-resistor formation. The embedding method and the heavily doped p-Si substrate have been employed to enhance the light emission from ZrHfO SSI-LEDs. Lastly, extensive applications of this novel nano-resistor device for on-chip optical interconnects and as diode-like anti-fuses have been discussed

Microelectronic Devices and Circuits - 2006 Electronic Edition

This book is based on the textbook Microelectronic Devices and Circuits by Clifton G. Fonstad, which was published by McGraw-Hill in 1994 (ISBN 0-07-021-496-4). McGraw-Hill has declared the original textbook “out of print” and has transferred the copyright to the author, Clifton G. Fonstad. Errata in the original text identified as of August 15, 2006 have been corrected in this edition. This edition will appear enlarged 110% from the original page size when printed on standard letter paper (8.5” x 11”).Combining semiconductor device physics and modeling with electronic circuit analysis and practice in a single sophomore/junior level microelectronics course, this textbook offers an integrated approach so students can truly understand the interaction between semiconductor physics, device structure, and integrated circuit design and operation. The balanced, modular treatments of bipolar and MOS devices, and of analog and digital circuits can be easily adapted to a particular instructor or class’s needs. SPICE models, MESFET’s, optoelectronic devices, worked examples, and end-of-the-chapter problems further enhance the text