A study of high-speed AD and DA converters using redundancy techniques Interim report, May 10, 1963 - May 9, 1964

High speed analog-to-digital converters compared using redundancy encoding technique

Development of a deep submicron fabrication process for tunneling field effect transistors

The requirements placed upon next-generation devices include high on-state current, low power supply voltages, and low subthreshold swing. Tunneling Field Effect Transistors (TFETs) have been of recent interest because they have the potential to fulfill these requirements. The TFET is a gated tunnel junction. The TFET operates by modulating the probability of band-to-band tunneling between the source and the channel of the device. When the tunnel transistor is off, there is a potential barrier between the source and the channel. The width of this potential barrier is large enough to prevent electrons tunneling from the valence to conduction bands, the result of which is a lower leakage current and improved power efficiency. The potential barrier narrows as bias is applied to the gate. When the applied gate voltage exceeds the threshold voltage this potential barrier becomes thin enough to allow for tunneling from the valence band to the conduction band. The tunneling mechanism allows the device to have a high on-state current and low subthreshold swing at low power supplies. To date the majority of the work involving TFETs has been simulation-based. Unfortunately the models used in these simulations are deficient. The models require physical data for proper calibration [1]. The few experimental demonstrations of TFETs have not yielded a body of empirical data sufficient for calibration. This work intends to help provide that body of experimental data on gated and non-gated tunneling junctions in InGaAs. This work focuses on the development of a process to gate p-i-n junctions and extract the contribution of the gate on junction performance

Quantum and spin-based tunneling devices for memory systems

Rapid developments in information technology, such as internet, portable computing, and wireless communication, create a huge demand for fast and reliable ways to store and process information. Thus far, this need has been paralleled with the revolution in solid-state memory technologies. Memory devices, such as SRAM, DRAM, and flash, have been widely used in most electronic products. The primary strategy to keep up the trend is miniaturization. CMOS devices have been scaled down beyond sub-45 nm, the size of only a few atomic layers. Scaling, however, will soon reach the physical limitation of the material and cease to yield the desired enhancement in device performance. In this thesis, an alternative method to scaling is proposed and successfully realized. The proposed scheme integrates quantum devices, Si/SiGe resonant interband tunnel diodes (RITD), with classical CMOS devices forming a microsystem of disparate devices to achieve higher performance as well as higher density. The device/circuit designs, layouts and masks involving 12 levels were fabricated utilizing a process that incorporates nearly a hundred processing steps. Utilizing unique characteristics of each component, a low-power tunneling-based static random access memory (TSRAM) has been demonstrated. The TSRAM cells exhibit bistability operation with a power supply voltage as low as 0.37 V. Various TSRAM cells were also constructed and their latching mechanisms have been extensively investigated. In addition, the operation margins of TSRAM cells are evaluated based on different device structures and temperature variation from room temperature up to 200oC. The versatility of TSRAM is extended beyond the binary system. Using multi-peak Si/SiGe RITD, various multi-valued TSRAM (MV-TSRAM) configurations that can store more than two logic levels per cell are demonstrated. By this virtue, memory density can be substantially increased. Using two novel methods via ambipolar operation and utilization of enable/disable transistors, a six-valued MV-TSRAM cell are demonstrated. A revolutionary novel concept of integrating of Si/SiGe RITD with spin tunnel devices, magnetic tunnel junctions (MTJ), has been developed. This hybrid approach adds non-volatility and multi-valued memory potential as demonstrated by theoretical predictions and simulations. The challenges of physically fabricating these devices have been identified. These include process compatibility and device design. A test bed approach of fabricating RITD-MTJ structures has been developed. In conclusion, this body of work has created a sound foundation for new research frontiers in four different major areas: integrated TSRAM system, MV-TSRAM system, MTJ/RITD-based nonvolatile MRAM, and RITD/CMOS logic circuits

The Journal of Microelectronic Research 2009

https://scholarworks.rit.edu/meec_archive/1017/thumbnail.jp

Solar energy conversion through the interaction of plasmons with tunnel junctions. Part A: Solar cell analysis. Part B: Photoconductor analysis

A solar cell utilizing guided optical waves and tunnel junctions was analyzed to determine its feasibility. From this analysis, it appears that the limits imposed upon conventional multiple cell systems also limit this solar cell. Due to this limitation, it appears that the relative simplicity of the conventional multiple cell systems over the solar cell make the conventional multiple cell systems the more promising candidate for improvement. It was discovered that some superlattice structures studied could be incorporated into an infrared photodetector. This photoconductor appears to be promising as a high speed, sensitive (high D sup star sub BLIP) detector in the wavelength range from 15 to over 100 micrometers

Cerium oxide based resistive random access memory devices

Resistive Random Access Memory (RRAM) is an emerging technology of non-volatile memory (NVM). Although the observation of metal oxide that can undergo an abrupt insulator-metal transition into a conductive state has been known for over 40 years, researchers started investigating those materials for memory applications in late 1990s. It has been considered as the next generation memory technology to replace current flash memory because RRAM has demonstrated feasible switching characteristics and potential to build high density arrays and also RRAM is also compatible with contemporary CMOS processes, which means RRAM can be integrated into current CMOS chips. While the structure of RRAM is a simple metal-insulator-metal (MIM) device, there are numerous materials that exhibit resistive switching. The switching behavior is not only dependent on the switching layer materials but also dependent on the choice of metal electrodes and their interfacial properties. Many metal oxides such as hafnium oxide, titanium oxide, aluminum oxide, nickel oxide (NiO), tantalum oxide and etc. have been studied in details; however, some materials are unexplored such as cerium oxide. In addition to nonvolatile storage applications, RRAM is considered as one of essential elements for advancing neuromorphic computing because of its analog switching and retention characteristics. This thesis investigated CeO[subscript x]-based RRAMs, from its fundamental device characteristics to neuromorphic applications.Electrical and Computer Engineerin

Integrated Circuits/Microchips

With the world marching inexorably towards the fourth industrial revolution (IR 4.0), one is now embracing lives with artificial intelligence (AI), the Internet of Things (IoTs), virtual reality (VR) and 5G technology. Wherever we are, whatever we are doing, there are electronic devices that we rely indispensably on. While some of these technologies, such as those fueled with smart, autonomous systems, are seemingly precocious; others have existed for quite a while. These devices range from simple home appliances, entertainment media to complex aeronautical instruments. Clearly, the daily lives of mankind today are interwoven seamlessly with electronics. Surprising as it may seem, the cornerstone that empowers these electronic devices is nothing more than a mere diminutive semiconductor cube block. More colloquially referred to as the Very-Large-Scale-Integration (VLSI) chip or an integrated circuit (IC) chip or simply a microchip, this semiconductor cube block, approximately the size of a grain of rice, is composed of millions to billions of transistors. The transistors are interconnected in such a way that allows electrical circuitries for certain applications to be realized. Some of these chips serve specific permanent applications and are known as Application Specific Integrated Circuits (ASICS); while, others are computing processors which could be programmed for diverse applications. The computer processor, together with its supporting hardware and user interfaces, is known as an embedded system.In this book, a variety of topics related to microchips are extensively illustrated. The topics encompass the physics of the microchip device, as well as its design methods and applications

Conference of Microelectronic Research 1999

https://scholarworks.rit.edu/meec_archive/1008/thumbnail.jp

Final Report on NASA Grant NAG 3-433. Solar Energy Conversion Through the Interaction of Plasmons with Tunnel Junctions. Part A Solar Cell Analysis. Part B Photoconductor Analysis

A novel solar cell utilizing guided optical waves and tunnel junctions has been analyzed to determine its feasibility. From this analysis, it appears that the limits imposed upon conventional multiple cell systems also limit this novel solar cell. Due to this limitation, it appears that the relative simplicity of the conventional multiple cell systems over the novel solar cell make the conventional multiple cell systems the more promising candidate for improvement. In the course of this investigation, it was discovered that some superlattice structures studied could be incorporated into an infrared photodetector. This photoconductor appears to be promising as a high speed, sensitive (high DBLip) detector in the wavelength range from 15 μm to over 100 μm