185 research outputs found
Recommended from our members
Versatile stochastic dot product circuits based on nonvolatile memories for high performance neurocomputing and neurooptimization.
The key operation in stochastic neural networks, which have become the state-of-the-art approach for solving problems in machine learning, information theory, and statistics, is a stochastic dot-product. While there have been many demonstrations of dot-product circuits and, separately, of stochastic neurons, the efficient hardware implementation combining both functionalities is still missing. Here we report compact, fast, energy-efficient, and scalable stochastic dot-product circuits based on either passively integrated metal-oxide memristors or embedded floating-gate memories. The circuit's high performance is due to mixed-signal implementation, while the efficient stochastic operation is achieved by utilizing circuit's noise, intrinsic and/or extrinsic to the memory cell array. The dynamic scaling of weights, enabled by analog memory devices, allows for efficient realization of different annealing approaches to improve functionality. The proposed approach is experimentally verified for two representative applications, namely by implementing neural network for solving a four-node graph-partitioning problem, and a Boltzmann machine with 10-input and 8-hidden neurons
An On-chip Trainable and Clock-less Spiking Neural Network with 1R Memristive Synapses
Spiking neural networks (SNNs) are being explored in an attempt to mimic
brain's capability to learn and recognize at low power. Crossbar architecture
with highly scalable Resistive RAM or RRAM array serving as synaptic weights
and neuronal drivers in the periphery is an attractive option for SNN.
Recognition (akin to reading the synaptic weight) requires small amplitude bias
applied across the RRAM to minimize conductance change. Learning (akin to
writing or updating the synaptic weight) requires large amplitude bias pulses
to produce a conductance change. The contradictory bias amplitude requirement
to perform reading and writing simultaneously and asynchronously, akin to
biology, is a major challenge. Solutions suggested in the literature rely on
time-division-multiplexing of read and write operations based on clocks, or
approximations ignoring the reading when coincidental with writing. In this
work, we overcome this challenge and present a clock-less approach wherein
reading and writing are performed in different frequency domains. This enables
learning and recognition simultaneously on an SNN. We validate our scheme in
SPICE circuit simulator by translating a two-layered feed-forward Iris
classifying SNN to demonstrate software-equivalent performance. The system
performance is not adversely affected by a voltage dependence of conductance in
realistic RRAMs, despite departing from linearity. Overall, our approach
enables direct implementation of biological SNN algorithms in hardware
Neuro-memristive Circuits for Edge Computing: A review
The volume, veracity, variability, and velocity of data produced from the
ever-increasing network of sensors connected to Internet pose challenges for
power management, scalability, and sustainability of cloud computing
infrastructure. Increasing the data processing capability of edge computing
devices at lower power requirements can reduce several overheads for cloud
computing solutions. This paper provides the review of neuromorphic
CMOS-memristive architectures that can be integrated into edge computing
devices. We discuss why the neuromorphic architectures are useful for edge
devices and show the advantages, drawbacks and open problems in the field of
neuro-memristive circuits for edge computing
In-memory computing with emerging memory devices: Status and outlook
Supporting data for "In-memory computing with emerging memory devices: status and outlook", submitted to APL Machine Learning
Highly Scalable Neuromorphic Hardware with 1-bit Stochastic nano-Synapses
Thermodynamic-driven filament formation in redox-based resistive memory and
the impact of thermal fluctuations on switching probability of emerging
magnetic switches are probabilistic phenomena in nature, and thus, processes of
binary switching in these nonvolatile memories are stochastic and vary from
switching cycle-to-switching cycle, in the same device, and from
device-to-device, hence, they provide a rich in-situ spatiotemporal stochastic
characteristic. This work presents a highly scalable neuromorphic hardware
based on crossbar array of 1-bit resistive crosspoints as distributed
stochastic synapses. The network shows a robust performance in emulating
selectivity of synaptic potentials in neurons of primary visual cortex to the
orientation of a visual image. The proposed model could be configured to accept
a wide range of nanodevices.Comment: 9 pages, 6 figure
Memristors: a short review on fundamentals, structures, materials and applications
The paper contains a short literature review on the subject of special type of thin film structures with resistive-switching memory effect. In the literature, such structures are commonly labeled as "memristors". The word "memristor" originates from two words: "memory" and "resistor". For the first time, the memristor was theoretically described in 1971 by Leon Chua as the 4th fundamental passive electronics element with a non-linear current-voltage behavior. The reported area of potential usage of memristor is enormous. It is predicted that the memristor could find application, for example in the domain of nonvolatile random access memory, flash memory, neuromorphic systems and so forth. However, in spite of the fact that plenty of papers have been published in the subject literature to date, the memristor still behaves as a "mysterious" electronic element. It seems that, one of the important reasons that such structures are not yet in practical use, is unsufficient knowledge of physical phenomena determining occurrence of the switching effect. The present paper contains a literature review of available descriptions of theoretical basis of the memristor structures, used materials, structure configurations and discussion about future prospects and limitations
Analog Spiking Neuromorphic Circuits and Systems for Brain- and Nanotechnology-Inspired Cognitive Computing
Human society is now facing grand challenges to satisfy the growing demand for computing power, at the same time, sustain energy consumption. By the end of CMOS technology scaling, innovations are required to tackle the challenges in a radically different way. Inspired by the emerging understanding of the computing occurring in a brain and nanotechnology-enabled biological plausible synaptic plasticity, neuromorphic computing architectures are being investigated. Such a neuromorphic chip that combines CMOS analog spiking neurons and nanoscale resistive random-access memory (RRAM) using as electronics synapses can provide massive neural network parallelism, high density and online learning capability, and hence, paves the path towards a promising solution to future energy-efficient real-time computing systems. However, existing silicon neuron approaches are designed to faithfully reproduce biological neuron dynamics, and hence they are incompatible with the RRAM synapses, or require extensive peripheral circuitry to modulate a synapse, and are thus deficient in learning capability. As a result, they eliminate most of the density advantages gained by the adoption of nanoscale devices, and fail to realize a functional computing system.
This dissertation describes novel hardware architectures and neuron circuit designs that synergistically assemble the fundamental and significant elements for brain-inspired computing. Versatile CMOS spiking neurons that combine integrate-and-fire, passive dense RRAM synapses drive capability, dynamic biasing for adaptive power consumption, in situ spike-timing dependent plasticity (STDP) and competitive learning in compact integrated circuit modules are presented. Real-world pattern learning and recognition tasks using the proposed architecture were demonstrated with circuit-level simulations. A test chip was implemented and fabricated to verify the proposed CMOS neuron and hardware architecture, and the subsequent chip measurement results successfully proved the idea.
The work described in this dissertation realizes a key building block for large-scale integration of spiking neural network hardware, and then, serves as a step-stone for the building of next-generation energy-efficient brain-inspired cognitive computing systems
- …