125 research outputs found
Capacity, Fidelity, and Noise Tolerance of Associative Spatial-Temporal Memories Based on Memristive Neuromorphic Network
We have calculated the key characteristics of associative
(content-addressable) spatial-temporal memories based on neuromorphic networks
with restricted connectivity - "CrossNets". Such networks may be naturally
implemented in nanoelectronic hardware using hybrid CMOS/memristor circuits,
which may feature extremely high energy efficiency, approaching that of
biological cortical circuits, at much higher operation speed. Our numerical
simulations, in some cases confirmed by analytical calculations, have shown
that the characteristics depend substantially on the method of information
recording into the memory. Of the four methods we have explored, two look
especially promising - one based on the quadratic programming, and the other
one being a specific discrete version of the gradient descent. The latter
method provides a slightly lower memory capacity (at the same fidelity) then
the former one, but it allows local recording, which may be more readily
implemented in nanoelectronic hardware. Most importantly, at the synchronous
retrieval, both methods provide a capacity higher than that of the well-known
Ternary Content-Addressable Memories with the same number of nonvolatile memory
cells (e.g., memristors), though the input noise immunity of the CrossNet
memories is somewhat lower
TCA<i>m</i>M<sup>CogniGron</sup>::Energy Efficient Memristor-Based TCAM for Match-Action Processing
The Internet relies heavily on programmable match-action processors for matching network packets against locally available network rules and taking actions, such as forwarding and modification of network packets. This match-action process must be performed at high speed, i.e., commonly within one clock cycle, using a specialized memory unit called Ternary Content Addressable Memory (TCAM). Building on transistor-based CMOS designs, state-of-the-art TCAM architectures have high energy consumption and lack resilient designs for incorporating novel technologies for performing appropriate actions. In this article, we motivate the use of a novel fundamental component, the ‘Memristor’, for the development of TCAM architecture for match-action processing. Memristors can provide energy efficiency, non-volatility and better resource density as compared to transistors. We have proposed a novel memristor-based TCAM architecture called TCAmMCogniGron, built upon the voltage divider principle and requiring only two memristors and five transistors for storage and search operations compared to sixteen transistors in the traditional TCAM architecture. We analyzed its performance over an experimental data set of Nb-doped SrTiO3-based memristor. The analysis of TCAmMCogniGron showed promising power consumption statistics of 16 uW and 1 uW for match and mismatch operations along with twice the improvement in resources density as compared to the traditional architectures
Large-scale memristive associative memories
Associative memories, in contrast to conventional address-based memories, are inherently fault-tolerant and allow retrieval of data based on partial search information. This paper considers the possibility of implementing large-scale associative memories through memristive devices jointly with CMOS circuitry. An advantage of a memristive associative memory is that the memory elements are located physically above the CMOS layer, which yields more die area for the processing elements realized in CMOS. This allows for high-capacity memories even while using an older CMOS technology, as the capacity of the memory depends more on the feature size of the memristive crossbar than on that of the CMOS components. In this paper, we propose the memristive implementations, and present simulations and error analysis of the autoassociative content-addressable memory, the Willshaw memory, and the sparse distributed memory. Furthermore, we present a CMOS cell that can be used to implement the proposed memory architectures.</div
Analog Feedback-Controlled Memristor programming Circuit for analog Content Addressable Memory
Recent breakthroughs in associative memories suggest that silicon memories
are coming closer to human memories, especially for memristive Content
Addressable Memories (CAMs) which are capable to read and write in analog
values. However, the Program-Verify algorithm, the state-of-the-art memristor
programming algorithm, requires frequent switching between verifying and
programming memristor conductance, which brings many defects such as high
dynamic power and long programming time. Here, we propose an analog
feedback-controlled memristor programming circuit that makes use of a novel
look-up table-based (LUT-based) programming algorithm. With the proposed
algorithm, the programming and the verification of a memristor can be performed
in a single-direction sequential process. Besides, we also integrated a single
proposed programming circuit with eight analog CAM (aCAM) cells to build an
aCAM array. We present SPICE simulations on TSMC 28nm process. The theoretical
analysis shows that 1. A memristor conductance within an aCAM cell can be
converted to an output boundary voltage in aCAM searching operations and 2. An
output boundary voltage in aCAM searching operations can be converted to a
programming data line voltage in aCAM programming operations. The simulation
results of the proposed programming circuit prove the theoretical analysis and
thus verify the feasibility to program memristors without frequently switching
between verifying and programming the conductance. Besides, the simulation
results of the proposed aCAM array show that the proposed programming circuit
can be integrated into a large array architecture
Memristive Computing
Memristive computing refers to the utilization of the memristor, the fourth
fundamental passive circuit element, in computational tasks.
The existence of the memristor was theoretically predicted in 1971 by
Leon O. Chua, but experimentally validated only in 2008 by HP Labs. A
memristor is essentially a nonvolatile nanoscale programmable resistor —
indeed, memory resistor — whose resistance, or memristance to be precise,
is changed by applying a voltage across, or current through, the device.
Memristive computing is a new area of research, and many of its fundamental
questions still remain open. For example, it is yet unclear which
applications would benefit the most from the inherent nonlinear dynamics
of memristors. In any case, these dynamics should be exploited to allow
memristors to perform computation in a natural way instead of attempting
to emulate existing technologies such as CMOS logic. Examples of such
methods of computation presented in this thesis are memristive stateful logic
operations, memristive multiplication based on the translinear principle, and
the exploitation of nonlinear dynamics to construct chaotic memristive circuits.
This thesis considers memristive computing at various levels of abstraction.
The first part of the thesis analyses the physical properties and the
current-voltage behaviour of a single device. The middle part presents memristor
programming methods, and describes microcircuits for logic and analog
operations. The final chapters discuss memristive computing in largescale
applications. In particular, cellular neural networks, and associative
memory architectures are proposed as applications that significantly benefit
from memristive implementation. The work presents several new results on
memristor modeling and programming, memristive logic, analog arithmetic
operations on memristors, and applications of memristors.
The main conclusion of this thesis is that memristive computing will
be advantageous in large-scale, highly parallel mixed-mode processing architectures.
This can be justified by the following two arguments. First,
since processing can be performed directly within memristive memory architectures,
the required circuitry, processing time, and possibly also power
consumption can be reduced compared to a conventional CMOS implementation.
Second, intrachip communication can be naturally implemented by
a memristive crossbar structure.Siirretty Doriast
X-TIME: An in-memory engine for accelerating machine learning on tabular data with CAMs
Structured, or tabular, data is the most common format in data science. While
deep learning models have proven formidable in learning from unstructured data
such as images or speech, they are less accurate than simpler approaches when
learning from tabular data. In contrast, modern tree-based Machine Learning
(ML) models shine in extracting relevant information from structured data. An
essential requirement in data science is to reduce model inference latency in
cases where, for example, models are used in a closed loop with simulation to
accelerate scientific discovery. However, the hardware acceleration community
has mostly focused on deep neural networks and largely ignored other forms of
machine learning. Previous work has described the use of an analog content
addressable memory (CAM) component for efficiently mapping random forests. In
this work, we focus on an overall analog-digital architecture implementing a
novel increased precision analog CAM and a programmable network on chip
allowing the inference of state-of-the-art tree-based ML models, such as
XGBoost and CatBoost. Results evaluated in a single chip at 16nm technology
show 119x lower latency at 9740x higher throughput compared with a
state-of-the-art GPU, with a 19W peak power consumption
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