A design for testability study on a high performance automatic gain control circuit.

A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presente

Design of a silicon cochlea system with biologically faithful response

This paper presents the design and simulation results of a silicon cochlea system that has closely similar behavior as the real cochlea. A cochlea filter-bank based on the improved three-stage filter cascade structure is used to model the frequency decomposition function of the basilar membrane; a filter tuning block is designed to model the adaptive response of the cochlea; besides, an asynchronous event-triggered spike codec is employed as the system interface with bank-end spiking neural networks. As shown in the simulation results, the system has biologically faithful frequency response, impulse response, and active adaptation behavior; also the system outputs multiple band-pass channels of spikes from which the original sound input can be recovered. The proposed silicon cochlea is feasible for analog VLSI implementation so that it not only emulates the way that sounds are preprocessed in human ears but also is able match the compact physical size of a real cochlea

Digitally-Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference

A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative “iterative” harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF, and 3.5 dBm in-band IIP3 while the out-of-band IIP3 is + 16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order HR > dB over 40 chips, while the digital AIC technique achieves HR > 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply

Discrete-Time Mixing Receiver Architecture for RF-Sampling Software-Defined Radio

A discrete-time (DT) mixing architecture for RF-sampling receivers is presented. This architecture makes RF sampling more suitable for software-defined radio (SDR) as it achieves wideband quadrature demodulation and wideband harmonic rejection. The paper consists of two parts. In the first part, different downconversion techniques are classified and compared, leading to the definition of a DT mixing concept. The suitability of CT-mixing and RF-sampling receivers to SDR is also discussed. In the second part, we elaborate the DT-mixing architecture, which can be realized by de-multiplexing. Simulation shows a wideband 90° phase shift between I and Q outputs without systematic channel bandwidth limitation. Oversampling and harmonic rejection relaxes RF pre-filtering and reduces noise and interference folding. A proof-of-concept DT-mixing downconverter has been built in 65 nm CMOS, for 0.2 to 0.9 GHz RF band employing 8-times oversampling. It can reject 2nd to 6th harmonics by 40 dB typically and without systematic channel bandwidth limitation. Without an LNA, it achieves a gain of -0.5 to 2.5 dB, a DSB noise figure of 18 to 20 dB, an IIP3 = +10 dBm, and an IIP2 = +53 dBm, while consuming less than 19 mW including multiphase clock generation