Investigation into digital circuit design with GaAs/Ga2O3 heterostructure MOSFETs

In this thesis, GaAs heterostructure MOSFETs are investigated as a potential technology for digital circuit design. The devices under investigation are 0.6 μm gate length, enhancement mode, heterostructure MOSFETs, with a high-κ dielectric (Ga2O3), and an InGaAs channel. Historically silicon CMOS technology has been the natural choice for digital circuits, however the realisation of GaAs MOSFET digital circuits could allow full integration of RF, optoelectronic and digital circuits on a single system-on-chip. Additionally, there are potential performance advantages in using GaAs due to it's high electron mobility. For the first time compact models of complimentary GaAs/Ga2O3 MOS are developed to enable an investigation into establishing a digital design methodology for GaAs MOS. Drift-diffusion models are developed and calibrated to measured device data. These models then provide information on the necessary device parameters to build compact models of these devices. BSIM3v3.2 compact models are developed based on this to enable GaAs MOS technology to be investigated using standard circuit design tools. The compact models have been adapted to ensure that they are physically relevant for GaAs devices. This includes some necessary approximations using effective medium theory. Further adjustments, or ratio corrections, are introduced to ensure that the internal physical parameters of BSIM will be correct. The models are compared to similarly-sized silicon devices to investigate the difference in performance between GaAs and silicon MOSFETs. As expected, the GaAs NMOS devices demonstrate improvements in drive current over silicon. However, the GaAs PMOS devices do not offer this advantage due to low hole mobility. Therefore, as a consequence of the high mobility ratio in GaAs, it is important to consider alternative digital design methodologies to CMOS to optimise performance. The performance of benchmark circuits is investigated for this technology in various digital design styles including CMOS, NMOS saturated enhancement load, and NMOS precharge. GaAs digital circuits gain a signifcant advantage in using alternative design styles to CMOS due to the relatively poor performance of the PMOS devices. In using the alternative styles the number of PMOS devices used can be minimised, and it is shown that NMOS precharge offers both speed and power advantages for this technology. The particular GaAs technology investigated does not outperform silicon in terms of speed and power. However, it has allowed a methodology to be established for future device generations, where performance is anticipated to improve signifcantly

Desenvolvimento de bancada virtual para simulação e monitorização de dispositivos de aquecimento de água

A controller for thermal systems is normally equipped with many facilities to make it flexible and the heating systems more cost-efficient. This results in a number of input parameters to be given by the user. It is not obvious how to choose appropriate values for these parameters unless the user has a large experience in this field. Water heating is a very important part of a household's energy use, and tankless gas water heaters (TGWH) are widely used. There are design and engineering challenges to develop more efficient devices, with lower emissions of pollutant gases and providing comfort improvements from the user point of view. Mathematical and semi-empirical models of the thermal systems were developed in order to simulate the dynamic models of water heating devices. A simulated environment is a less expensive and fastest way of evaluating the relative merits of different control schemes for a given thermal system. A technique to accelerate the process for developing controllers was implemented. Hardware-in-the-loop simulation (HILS) has proved to be very useful to test hardware controllers in virtual environments simulated in real-time. In the scope of the Smart Green Homes Project, a virtual test bench with a TGWH was proposed to support the multiple phases of controller's development, whether it is to control a real or a virtual system. The experimental platform was developed to test the implemented hybrid models performance in hardware-in-the-loop simulation experiences. The platform is composed by a TGWH with a group of sensors, by real-time hardware and by a package of software tools for data acquisition and control. In the final stage of this work, two case studies were carried out, in which the first was dedicated to the validation of the virtual bench concept and the second was to control and monitor a water heating device. Very satisfactory results, from a set of HILS experiences performed in real-time simulations, were obtained for the semi-empirical models proposed.Um controlador para sistemas térmicos está normalmente equipado com muitas instalações para o tornar flexível e os sistemas de aquecimento mais económicos. Isto resulta numa série de parâmetros de entrada a serem dados pelo utilizador. Não é óbvio como escolher valores apropriados para estes parâmetros, a menos que o utilizador tenha uma grande experiência neste campo. O aquecimento de água é uma parte muito importante do consumo de energia de um agregado familiar, e os aquecedores de água a gás sem tanque (TGWH) são amplamente utilizados. Há desafios de projeto e engenharia para desenvolver dispositivos mais eficientes, com menores emissões de gases poluentes e proporcionando melhorias de conforto do ponto de vista do utilizador. Foram desenvolvidos modelos matemáticos e semi-empíricos dos sistemas térmicos para simular os modelos dinâmicos dos dispositivos de aquecimento de água. Um ambiente simulado é uma forma menos dispendiosa e mais rápida de avaliar os méritos relativos de diferentes esquemas de controle para um determinado sistema térmico. Foi implementada uma técnica para acelerar o processo de desenvolvimento de controladores. A simulação Hardware-in-the-loop (HILS) provou ser muito útil para testar controladores de hardware em ambientes virtuais simulados em tempo real. No âmbito do projecto Smart Green Homes, foi proposta uma bancada de ensaios virtual com um TGWH para apoiar as múltiplas fases de desenvolvimento do controlador, seja para controlar um sistema real ou virtual. A plataforma experimental foi desenvolvida para testar o desempenho dos modelos híbridos implementados em experiências de simulação hardware-in-the-loop. A plataforma é composta por um TGWH com um grupo de sensores, por hardware em tempo real e por um pacote de ferramentas de software para aquisição e controlo de dados. Na fase final deste trabalho, foram realizados dois estudos de caso, em que o primeiro foi dedicado à validação do conceito da bancada virtual e o segundo foi para controlar e monitorizar um dispositivo de aquecimento de água. Foram obtidos resultados muito satisfatórios, a partir de um conjunto de experiências HILS realizadas em simulações em tempo real, para os modelos semi-empíricos propostos.Mestrado em Engenharia Mecânic

Fine-grained Energy and Thermal Management using Real-time Power Sensors

With extensive use of battery powered devices such as smartphones, laptops an

Design of event-driven automatic gain control and high-speed data path for multichannel optical receiver arrays

The internet has become the ubiquitous tool that has transformed the lives of all of us. New broadband applications in the field of entertainment, commerce, industry, healthcare and social interactions demand increasingly higher data rates and quality of the networks and ICT infrastructure. In addition, high definition video streaming and cloud services will continue to push the demand for bandwidth. These applications are reshaping the internet into a content-centric network. The challenge is to transform the telecom optical networks and data centers such that they can be scaled efficiently, at low cost. Furthermore, from both an environmental and economic perspective, this scaling should go hand in hand with reduced power consumption. This stems from the desire to reduce CO2 emission and to reduce network operating costs while offering the same service level as today. In the current architecture of the internet, end-users connect to the public network using the access network of an internet service provider (ISP). Today, this access network either reuses the legacy copper or coaxial network or uses passive optical network (PON) technologies, among which the PON is the most energy efficient and provides the highest data rates. Traffic from the access network is aggregated with Ethernet switches and routed to the core network through the provider edge routers, with broadband network gateways (BNGs) to regulate access and usage. These regional links are collectively called the metro network. Data centers connect to the core network using their own dedicated gateway router. The problem of increasing data rates, while reducing the economic and environmental impact, has attracted considerable attention. The research described in this work has been performed in the context of two projects part of the European Union Seventh Framework Programme (FP7), which both aim for higher data rates and tight integration while keeping power consumption low. Mirage targets data center applications while C3PO focuses on medium-reach networks, such as the metro network. Specifically, this research considers two aspects of the high-speed optical receivers used in the communication networks: increasing dynamic range of a linear receiver for multilevel modulation through automatic gain control (AGC) and integration of multiple channels on a single chip with a small area footprint. The data centers of today are high-density computing facilities that provide storage, processing and software as a service to the end-user. They are comprised of gateway routers, a local area network, servers and storage. All of this is organized in racks. The largest units contain over 100 000 servers. The major challenges regarding data centers are scalability and keeping up with increasing amounts of traffic while reducing power consumption (of the devices as well as the associated cooling) and keeping cost minimal. Presently, racks are primarily interconnected with active optical cables (AOCs) which employ signal rates up to 25 Gb/s per lane with non-return-to-zero (NRZ) modulation. A number of technological developments can be employed in AOCs of the future to provide terabit-capacity optical interconnects over longer distances. One such innovation is the use of multilevel modulation formats, which are more bandwidth-efficient than traditional NRZ modulation. Multilevel modulation requires a linear amplifier as front-end of the optical receiver. The greater part of this dissertation discusses the design and implementation of an AGC system for the data path of a linear transimpedance amplifier (TIA). The metro network is the intermediate regional network between the access and core network of the internet architecture, with link lengths up to 500 km. It is estimated that in the near future metro-traffic will increase massively. This growth is attributed mainly to increasing traffic from content delivery networks (CDNs) and data centers, which bypass the core network and directly connect to the metro network. Internet video growth is the major reason for traffic increase. This evolution demands increasingly higher data rates. Today, dense wavelength division multiplexing (DWDM) is widely recognized as being necessary to provide data capacity scalability for future optical networks, as it allows for much higher combined data rates over a single fiber. At the receiver, each wavelength of the demultiplexed incoming light is coupled to a photo diode in a photo diode array which is connected to a dedicated lane of a multichannel receiver. The high number of channels requires small physical channel spacing and tight integration of the diode array with the receiver. In addition, active cooling should be avoided, such that power consumption per receiver lane must be kept low in order not to exceed thermal operation limits. The second component of this work presents the development of an integrated four-channel receiver, targeting 4 × 25 Gb/s data rate, with low power consumption and small footprint to support tight integration with a p-i-n photo diode array with a 250 μm channel pitch. Chapter 1 discusses the impact of increasing data rates and the desire to reduce power consumption on the design of the optical receiver component, in wide metropolitan area networks as well as in short-reach point-to-point links in data centers. In addition, some aspects of integrated analog circuit design are highlighted: the design flow, transistor hand models, a software design tool. Also, an overview of the process technology is given. Chapter 2 provides essential optical receiver concepts, which are required to understand the remainder of the work. Fundamentals of feedback AGC systems are discussed in the first part of Chapter 3. A basic system model is presented in the continuous-time domain, in which the variable gain amplifier (VGA) constitutes the multistage datapath of a linear optical receiver. To enable reliable reception of multilevel modulation formats, the VGA requires controlled frequency response and in particular limited time-domain overshoot across the gain range. It is argued that this control is hard to achieve with fully analog building blocks. Therefore, an event-driven approach is proposed as an extension of the continuous-time system. Both the structural and behavioral aspects are discussed. The result is a system model of a quantized AGC loop, upon which the system-level design, presented in Chapter 4, is based. In turn, Chapter 5 discusses the detailed implementation of the various building blocks on the circuit level and presents experimental results that confirm the feasibility of the proposed approach. Chapter 6 discusses the design and implementation of a 4 × 25 Gb/s optical receiver array for NRZ modulation with a small area footprint. The focus lies on the input stages and techniques to extend bandwidth and dynamic range are presented. Measurement results for NRZ and optical duobinary (ODB) modulation are presented, as well as the influence of crosstalk on the performance. Finally, Chapter 7 provides an overview of the foremost conclusions of the presented research and includes suggestions for future research. Two appendices are included. Appendix A gives an overview of the general network theorem (GNT), which is used throughout this work and which has been implemented numerically. The results from Appendix B, the analysis of a two-stage opamp compensated with capacitance multipliers, were used to design a building block for the AGC system

Novel linear and nonlinear optical signal processing for ultra-high bandwidth communications

The thesis is articulated around the theme of ultra-wide bandwidth single channel signals. It focuses on the two main topics of transmission and processing of information by techniques compatible with high baudrates. The processing schemes introduced combine new linear and nonlinear optical platforms such as Fourier-domain programmable optical processors and chalcogenide chip waveguides, as well as the concept of neural network. Transmission of data is considered in the context of medium distance links of Optical Time Division Multiplexed (OTDM) data subject to environmental fluctuations. We experimentally demonstrate simultaneous compensation of differential group delay and multiple orders of dispersion at symbol rates of 640 Gbaud and 1.28 Tbaud. Signal processing at high bandwidth is envisaged both in the case of elementary post-transmission analog error mitigation and in the broader field of optical computing for high level operations (“optical processor”). A key innovation is the introduction of a novel four-wave mixing scheme implementing a dot-product operation between wavelength multiplexed channels. In particular, it is demonstrated for low-latency hash-key based all-optical error detection in links encoded with advanced modulation formats. Finally, the work presents groundbreaking concepts for compact implementation of an optical neural network as a programmable multi-purpose processor. The experimental architecture can implement neural networks with several nodes on a single optical nonlinear transfer function implementing functions such as analog-to-digital conversion. The particularity of the thesis is the new approaches to optical signal processing that potentially enable high level operations using simple optical hardware and limited cascading of components

Multi-band Oversampled Noise Shaping Analog to Digital Conversion

Oversampled noise shaping analog to digital (A/D) converters, which are commonly known as delta-sigma (ΔΣ) converters, have the ability to convert relatively low bandwidth signals with very high resolution. Such converters achieve their high resolution by oversampling, as well as processing the signal and quantization noise with different transfer functions. The signal transfer function (STF) is typically a delay over the signal band while the noise transfer function (NTF) is designed to attenuate quantization noise in the signal band. A side effect of the NTF is an amplification of the noise outside the signal band. Thus, a digital filter subsequently attenuates the out-of-band quantization noise. The focus of this thesis is the investigation of ΔΣ architectures that increase the bandwidth where high resolution conversion can be achieved. It uses parallel architectures exploiting frequency or time slicing to meet this objective. Frequency slicing involves quantizing different portions of the signal frequency spectrum using several quantizers in parallel and then combining the results of the quantizers to form an overall result. Time slicing involves quantizing various groups of time domain signal samples with different quantizers in parallel and then combining the results of the quantizers to form an overall output. Several interesting observations can be made from this general perspective of frequency and time slicing. Although the representation of a signal are completely equivalent in time or frequency, the thesis shows that this is not the case for known frequency and time sliced A/D architectures. The performance of such systems under ideal conditions are compared for PCM as well as for ΔΣ A/D converters. A multi-band frequency sliced architecture for delta-sigma conversion is proposed and its performance is included in the above comparison. The architecture uses modulators which realize different NTFs for different portions of the signal band. Each band is converted in parallel. A bank of FIR filters attenuates the out of-band noise for each band and achieves perfect reconstruction of the signal component. A design procedure is provided for the design of the filter bank with reduced computational complexity. The use of complex NTFs in the multi-band ΔΣ architecture is also proposed. The peformance of real and complex NTFs is compared. Performance evaluations are made for ideal systems as well as systems suffering from circuit implementation imperfections such as finite opamp gain and mismatched capacitor ratios

Study and implementation of an advanced transceiver for 5G

With the years passing by, the users of mobile networks present higher needs and demands when it comes to e ective download and upload data rates. The fth generation of mobile communications assumes the concretization of binary rates above 1 Gbps to be achieved by any ordinary user. To ful l this requirement, it was necessary to undertake a study and development of a system using the 4th Generation of Mobile Communications (4G) waveform to lessen the need for adding new modules and increasing the complexity of mobile network systems. The main goal is to develop an Orthogonal Frequency Division Multiplexing (OFDM) waveform simulator for 5th Generation of Mobile Communications (5G) using Quadrature Amplitude Modulation (QAM), simulate its performance to compare with the theoretical one and perform laboratorial tests. In this study the channel estimation is carried out and we evaluated the performance of Bit Error Rate (BER) and Error Vector Magnitude (EVM) as study metrics and parallels the usual transmission loss models for indoor and free-space communications. The study and experiments end in resulting mobile uncoded and convolutional hard decision OFDM communications up to 5.9 Gbps of e ective data rate and the results and measurements were obtained inside the laboratory environment, with a signal carrier of 3.5GHz and 2dB of both antennas gain and 26dB of ampli er gain at distances up to 4 meters between the two antennas. The best result obtained considering the highest data rate achieved was a 256-QAM uncoded OFDM communication at 5.9 Gbps on a 4 meters distance between antennas.A quinta geração de redes móveis prevê a concretização de ritmos binários acima de 1 Gbps ao acesso de qualquer utilizador comum. Para concretizar esse requisito, foi necessário levar a cargo um estudo e desenvolvimento de um sistema que utilize a forma de onda do 4a Geração de Comunicações Móveis (4G) para diminuir eventuais necessidades de adição de novos módulos e aumento da complexidade dos sistemas de redes móveis. O objetivo concreto é o desenvolvimento de um simulador de forma de onda de Multiplexação por Divisão de Frequência Ortogonal (OFDM) que atinja as taxas efetivas de dados para a 5a Geração de Comunicações Móveis (5G) utilizando Modulação de Amplitude em Quadratura (QAM), realizar simulações para averiguar o normal funcionamento de acordo com a teoria e realizar testes laboratoriais. Neste estudo é efetuada a estimação de canal, são avaliadas as performances da Taxa de Erro de Bits (BER) e da Magnitude do Vetor de Erro (EVM) como métricas de estudo e efetuado um paralelismo com os modelos de perdas de transmissão usuais para comunicações indoor e de espaço livre. O estudo e os testes laboratoriais concluem-se em comunicações OFDM não codi cado e com decisão abrupta em códigos convolucionais efetuadas até velocidades efetivas de 5.9 Gbps de dados e foram obtidos os resultados e medições num ambiente de laboratório, com uma portadora de 3.5 GHz, com o ganho de ambas as antenas de 2dB e um ampli cador com um ganho de 26dB em distâncias até aos 4 metros entre as duas antenas. O melhor resultado obtido em termos de velocidade de transmissão de dados foi a comunicação 256-QAM OFDM não codi cado atingindo os 5.9 Gbps com 4 metros de distância entre antenas

3D drift diffusion and 3D Monte Carlo simulation of on-current variability due to random dopants

In this work Random Discrete Dopant induced on-current variations have been studied using the Glasgow 3D atomistic drift/diffusion simulator and Monte Carlo simulations. A methodology for incorporating quantum corrections into self-consistent atomistic Monte Carlo simulations via the density gradient effective potential is presented. Quantum corrections based on the density gradient formalism are used to simultaneously capture quantum confinement effects. The quantum corrections not only capture charge confinement effects, but accurately represent the electron impurity interaction used in previous \textit{ab initio} atomistic MC simulations, showing agreement with bulk mobility simulation. The effect of quantum corrected transport variation in statistical atomistic MC simulation is then investigated using a series of realistic scaled devices nMOSFETs transistors with channel lengths 35 nm, 25 nm, 18nm, 13 nm and 9 nm. Such simulations result in an increased drain current variability when compared with drift diffusion simulation. The comprehensive statistical analysis of drain current variations is presented separately for each scaled transistor. The investigation has shown increased current variation compared with quantum corrected drift diffusion simulation and with previous classical MC results. Furthermore, it has been studied consistently the impact of transport variability due to scattering from random discrete dopants on the on-current variability in realistic nano CMOS transistors. For the first time, a hierarchic simulation strategy to accurately transfer the increased on-current variability obtained from the ‘ab initio’ MC simulations to DD simulations is subsequently presented. The MC corrected DD simulations are used to produce target $I_D-V_G$ characteristics from which statistical compact models are extracted for use in preliminary design kits at the early stage of new technology development. The impact of transport variability on the accuracy of delay simulation are investigated in detail. Accurate compact models extraction methodology transferring results from accurate physical variability simulation into statistical compact models suitable for statistical circuit simulation is presented. In order to examine te size of this effect on circuits Monte Carlo SPICE simulations of inverter were carried out for 100 samples