A Review of Bayesian Methods in Electronic Design Automation

The utilization of Bayesian methods has been widely acknowledged as a viable solution for tackling various challenges in electronic integrated circuit (IC) design under stochastic process variation, including circuit performance modeling, yield/failure rate estimation, and circuit optimization. As the post-Moore era brings about new technologies (such as silicon photonics and quantum circuits), many of the associated issues there are similar to those encountered in electronic IC design and can be addressed using Bayesian methods. Motivated by this observation, we present a comprehensive review of Bayesian methods in electronic design automation (EDA). By doing so, we hope to equip researchers and designers with the ability to apply Bayesian methods in solving stochastic problems in electronic circuits and beyond.Comment: 24 pages, a draft version. We welcome comments and feedback, which can be sent to [email protected]

A verification technique for multiple soft fault diagnosis of linear analog circuits

The paper deals with multiple soft fault diagnosis of linear analog circuits. A fault verification method is developed that allows estimating the values of a set of the parameters considered as potentially faulty. The method exploits the transmittance of the circuit and is based on a diagnostic test leading to output signal in discrete form. Applying Z-transform a diagnostic equation is written which is next reproduced. The obtained system of equations consisting of larger number of equations than the number of the parameters is solved using appropriate numerical approach. The method is adapted to real circumstances taking into account scattering of the fault–free parameters within their tolerance ranges and some errors produced by the method. In consequence, the results provided by the method have the form of ranges including the values of the tested parameters. To illustrate the method two examples of real electronic circuits are given

Performance monitoring of aircraft PMSM based on soft computing technique

Rigorous fault analysis (FA) referring to fault detection its level is important for maintenances to simplify as well as improves performance. The purpose of this study was to present a technique for the electronic diagnosis of switch defects in regular magnetic concurrent motors (PMSM) For Aircraft application. The performance level of the bridges of the thyristor and the device excitation diode is tracked in healthy and defective service processes. Extracted functionality in various procedures that use Decomposition of the Multi-Scale Wavelet (MSWD) to remove useful functionality. The functionalities of the MSWD are utilized to train the Autoregressive of the Nonlinear with Exogenous Model (NARX) that was Sequence of the method controlled to determine the level of the fault in an open circuit forming through a switch. Both models were evaluated and built based on simulated data, where the findings demonstrated a preferable efficacy in the diagnosis of different kinds of fault

FPGAs in Industrial Control Applications

The aim of this paper is to review the state-of-the-art of Field Programmable Gate Array (FPGA) technologies and their contribution to industrial control applications. Authors start by addressing various research fields which can exploit the advantages of FPGAs. The features of these devices are then presented, followed by their corresponding design tools. To illustrate the benefits of using FPGAs in the case of complex control applications, a sensorless motor controller has been treated. This controller is based on the Extended Kalman Filter. Its development has been made according to a dedicated design methodology, which is also discussed. The use of FPGAs to implement artificial intelligence-based industrial controllers is then briefly reviewed. The final section presents two short case studies of Neural Network control systems designs targeting FPGAs

Fault-based Analysis of Industrial Cyber-Physical Systems

The fourth industrial revolution called Industry 4.0 tries to bridge the gap between traditional Electronic Design Automation (EDA) technologies and the necessity of innovating in many indus- trial fields, e.g., automotive, avionic, and manufacturing. This complex digitalization process in- volves every industrial facility and comprises the transformation of methodologies, techniques, and tools to improve the efficiency of every industrial process. The enhancement of functional safety in Industry 4.0 applications needs to exploit the studies related to model-based and data-driven anal- yses of the deployed Industrial Cyber-Physical System (ICPS). Modeling an ICPS is possible at different abstraction levels, relying on the physical details included in the model and necessary to describe specific system behaviors. However, it is extremely complicated because an ICPS is com- posed of heterogeneous components related to different physical domains, e.g., digital, electrical, and mechanical. In addition, it is also necessary to consider not only nominal behaviors but even faulty behaviors to perform more specific analyses, e.g., predictive maintenance of specific assets. Nevertheless, these faulty data are usually not present or not available directly from the industrial machinery. To overcome these limitations, constructing a virtual model of an ICPS extended with different classes of faults enables the characterization of faulty behaviors of the system influenced by different faults. In literature, these topics are addressed with non-uniformly approaches and with the absence of standardized and automatic methodologies for describing and simulating faults in the different domains composing an ICPS. This thesis attempts to overcome these state-of-the-art gaps by proposing novel methodologies, techniques, and tools to: model and simulate analog and multi-domain systems; abstract low-level models to higher-level behavioral models; and monitor industrial systems based on the Industrial Internet of Things (IIOT) paradigm. Specifically, the proposed contributions involve the exten- sion of state-of-the-art fault injection practices to improve the ICPSs safety, the development of frameworks for safety operations automatization, and the definition of a monitoring framework for ICPSs. Overall, fault injection in analog and digital models is the state of the practice to en- sure functional safety, as mentioned in the ISO 26262 standard specific for the automotive field. Starting from state-of-the-art defects defined for analog descriptions, new defects are proposed to enhance the IEEE P2427 draft standard for analog defect modeling and coverage. Moreover, dif- ferent techniques to abstract a transistor-level model to a behavioral model are proposed to speed up the simulation of faulty circuits. Therefore, unlike the electrical domain, there is no extensive use of fault injection techniques in the mechanical one. Thus, extending the fault injection to the mechanical and thermal fields allows for supporting the definition and evaluation of more reliable safety mechanisms. Hence, a taxonomy of mechanical faults is derived from the electrical domain by exploiting the physical analogies. Furthermore, specific tools are built for automatically instru- menting different descriptions with multi-domain faults. The entire work is proposed as a basis for supporting the creation of increasingly resilient and secure ICPS that need to preserve functional safety in any operating context

HEALTH ESTIMATION AND REMAINING USEFUL LIFE PREDICTION OF ELECTRONIC CIRCUIT WITH A PARAMETRIC FAULT

Degradation of electronic components is typically accompanied by a deviation in their electrical parameters from their initial values. Such parametric drifts in turn will cause degradation in performance of the circuit they are part of, eventually leading to function failure due to parametric faults. The existing approaches for predicting failures resulting from electronic component parametric faults emphasize identifying monotonically deviating parameters and modeling their progression over time. However, in practical applications where the components are integrated into a complex electronic circuit assembly, product or system, it is generally not feasible to monitor component-level parameters. To address this problem, a prognostics method that exploits features extracted from responses of circuit-comprising components exhibiting parametric faults is developed in this dissertation. The developed prognostic method constitutes a circuit health estimation step followed by a degradation modeling and remaining useful life (RUL) prediction step. First, the circuit health estimation method was developed using a kernel-based machine learning technique that exploits features that are extracted from responses of circuit-comprising components exhibiting parametric faults, instead of the component-level parameters. The performance of kernel learning technique depends on the automatic adaptation of hyperparameters (i.e., regularization and kernel parameters) to the learning features. Thus, to achieve high accuracy in health estimation the developed method also includes an optimization method that employs a penalized likelihood function along with a stochastic filtering technique for automatic adaptation of hyperparameters. Second, the prediction of circuit’s RUL is realized by a model-based filtering method that relies on a first principles-based model and a stochastic filtering technique. The first principles-based model describes the degradation in circuit health with progression of parametric fault in a circuit component. The stochastic filtering technique on the other hand is used to first solve a joint ‘circuit health state—parametric fault’ estimation problem, followed by prediction problem in which the estimated ‘circuit health state—parametric fault’ is propagated forward in time to predict RUL. Evaluations of the data from simulation experiments on a benchmark Sallen–Key filter circuit and a DC–DC converter system demonstrate the ability of the developed prognostic method to estimate circuit health and predict RUL without having to monitor the individual component parameters

AI/ML Algorithms and Applications in VLSI Design and Technology

An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations

Cost-Effective Reduced Envelope of the Stator Current via Synchronous Sampling for the Diagnosis of Rotor Asymmetries in Induction Machines Working at Very Low Slip

[EN] Fault diagnosis of rotor asymmetries of induction machines (IMs) using the stator current relies on the detection of the characteristic signatures of the fault harmonics in the current spectrum. In some scenarios, such as large induction machines running at a very low slip, or unloaded machines tested offline, this technique may fail. In these scenarios, the fault harmonics are very close to the frequency of the fundamental component, and have a low amplitude, so that they may remain undetected, buried under the fundamental's leakage, until the damage is severe. To avoid false positives, a proven approach is to search for the fault harmonics in the current envelope, instead of the current itself, because in this case the spectrum is free from the leakage of the fundamental. Besides, the fault harmonics appear at a very low frequency. Nevertheless, building the current spectrum is costly in terms of computing complexity, as in the case of the Hilbert transform, or hardware resources, as in the need for simultaneously sampling three stator currents in the case of the extended current Park's vector approach (EPVA). In this work, a novel method is proposed to avoid this problem. It is based on sampling a phase current just twice per current cycle, with a fixed delay with respect to its zero crossings. It is shown that the spectrum of this reduced set of current samples contains the same fault harmonics as the spectrum of the full-length current envelope, despite using a minimal amount of computing resources. The proposed approach is cost-effective, because the computational requirements for building the current envelope are reduced to less than 1% of those required by other conventional methods, in terms of storage and computing time. In this way, it can be implemented with low-cost embedded devices for on-line fault diagnosis. The proposed approach is introduced theoretically and validated experimentally, using a commercial induction motor with a broken bar under different load and supply conditions. Besides, the proposed approach has been implemented on a low-cost embedded device, which can be accessed on-line for remote fault diagnosis.This research was funded by the Spanish "Ministerio de Ciencia, Innovacion y Universidades (MCIU)", the "Agencia Estatal de Investigacion (AEI)" and the "Fondo Europeo de Desarrollo Regional (FEDER)" in the framework of the "Proyectos I+D+i - Retos Investigacion 2018", project reference RTI2018-102175-B-I00 (MCIU/AEI/FEDER, UE).Burriel-Valencia, J.; Puche-Panadero, R.; Martinez-Roman, J.; Sapena-Bano, A.; Pineda-Sanchez, M. (2019). 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