Designing a CPU model: from a pseudo-formal document to fast code

For validating low level embedded software, engineers use simulators that take the real binary as input. Like the real hardware, these full-system simulators are organized as a set of components. The main component is the CPU simulator (ISS), because it is the usual bottleneck for the simulation speed, and its development is a long and repetitive task. Previous work showed that an ISS can be generated from an Architecture Description Language (ADL). In the work reported in this paper, we generate a CPU simulator directly from the pseudo-formal descriptions of the reference manual. For each instruction, we extract the information describing its behavior, its binary encoding, and its assembly syntax. Next, after automatically applying many optimizations on the extracted information, we generate a SystemC/TLM ISS. We also generate tests for the decoder and a formal specification in Coq. Experiments show that the generated ISS is as fast and stable as our previous hand-written ISS.Comment: 3rd Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (2011

Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator

Abstract. Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. State-of-the-art simulators using just-in-time (JIT) dynamic binary translation (DBT) techniques are able to simulate complex embedded processors at speeds above 500 MIPS. However, these functional ISS do not provide microarchitectural observability. In contrast, low-level cycle-accurate ISS are too slow to simulate full-scale applications, forcing developers to revert to FPGA-based simulations. In this paper we demonstrate that it is possible to run ultra-high speed cycle-accurate instruction set simulations surpassing FPGA-based simulation speeds. We extend the JIT DBT engine of our ISS and augment JIT generated code with a verified cycle-accurate processor model. Our approach can model any microarchitectural configuration, does not rely on prior profiling, instrumentation, or compilation, and works for all binaries targeting a state-of-the-art embedded processor implementing the ARCompact TM instruction set architecture (ISA). We achieve simulation speeds up to 88 MIPS on a standard x86 desktop computer for the industry standard EEMBC, COREMARK and BIOPERF benchmark suites.

From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

Performance Debugging and Tuning using an Instruction-Set Simulator

Instruction-set simulators allow programmers a detailed level of insight into, and control over, the execution of a program, including parallel programs and operating systems. In principle, instruction set simulation can model any target computer and gather any statistic. Furthermore, such simulators are usually portable, independent of compiler tools, and deterministic-allowing bugs to be recreated or measurements repeated. Though often viewed as being too slow for use as a general programming tool, in the last several years their performance has improved considerably. We describe SIMICS, an instruction set simulator of SPARC-based multiprocessors developed at SICS, in its rôle as a general programming tool. We discuss some of the benefits of using a tool such as SIMICS to support various tasks in software engineering, including debugging, testing, analysis, and performance tuning. We present in some detail two test cases, where we've used SimICS to support analysis and performance tuning of two applications, Penny and EQNTOTT. This work resulted in improved parallelism in, and understanding of, Penny, as well as a performance improvement for EQNTOTT of over a magnitude. We also present some early work on analyzing SPARC/Linux, demonstrating the ability of tools like SimICS to analyze operating systems

Network-aware design-space exploration of a power-efficient embedded application

The paper presents the design and multi-parameter optimization of a networked embedded application for the health-care domain. Several hardware, software, and application parameters, such as clock frequency, sensor sampling rate, data packet rate, are tuned at design- and run-time according to application specifications and operating conditions to optimize hardware requirements, packet loss, power consumption. Experimental results show that further power efficiency can be achieved by considering also communication aspects during design space exploratio

An interactive and pen-based simulator to enhance education and research in computer systems: An experience report

The active uses of simulators to facilitate and/or promote learners’ experience in many applications has significantly reshaped the latest educational technology or training methodologies in the past decades including the training of engineering students to understand the actual working mechanisms of specific engineering principles, or the military officers on tactic planning in a simulated combat environment. In many cases, it was clearly revealed that the appropriate uses of simulators not only avoids the indispensable costs of human lives or money lost in the hostile combat or investment field, but also effectively motivates and/or enhances the learners’ interests in the relevant fields of study, thus fueling significant impacts on their actual performance. However, many conventional simulators often require the users to input a formal specification file such as a script or program to specify about the simulation settings. Besides, even in many Window based simulators, the users may need to explicitly memorize about the meanings of various system variables and their proper settings before running a simulation to observe the imparted changes. All these unnecessary hassles will drastically reduce the interactivity of simulators, and also lower the users’ interests in using them. With the fast developing tablet and ultra-mobile PCs, we have seen ample opportunities of employing sophisticated pen-based computing technologies to improve the interactivity of simulators in order to enhance the learners’ experience to learn, reason or visualize with simulators in more effective ways. Therefore, in a recent pen-based simulator development project awarded by the Microsoft Research Asia (MSRA), we proposed to use the Microsoft digital ink library to support fast symbol/character recognition and the XML technologies to flexibly define various models of computer architectures so as to build an innovative and pen-based simulator for mobile computing devices. With pen-based or other inputs, our simulator allows the instructors/students to flexibly add or modify instructions that will generate live animations to facilitate interactive discussion for teaching undergraduate to postgraduate courses. Besides, our simulator has the full potential to support research on computer systems through visualization of new results generated out of new computational models or optimization strategies. A prototype of our simulator was completed and then released to all our Year-1 students for trials in the last month in which we collected some initial and positive feedbacks. A more vigorous evaluation was planned and would be conducted by the end of this spring semester. All in all, there are many interesting directions for further investigation including the integration of relevant course materials in the form of digital resources or pointers to online databases into our simulator, and a careful study of the pedagogical changes brought by our innovative and pen-based simulator.published_or_final_versio