Development of 20 GHz monolithic transmit modules

The history of the development of a transmit module for the band 17.7 to 20.2 GHz is presented. The module was to monolithically combine, on one chip, five bits of phase shift, a buffer amplifier and a power amplifier to produce 200 mW to the antenna element. The approach taken was MESFET ion implanted device technology. A common pinch-off voltage was decided upon for each application. The beginning of the total integration phases revealed hitherto unencountered hazards of large microwave circuit integration which were successfully overcome. Yield and customer considerations finally led to two separate chips, one containing the power amplifiers and the other containing the complete five bit phase shifter

Low-Overhead Built-In Self-Test for Advanced RF Transceiver Architectures

abstract: Due to high level of integration in RF System on Chip (SOC), the test access points are limited to the baseband and RF inputs/outputs of the system. This limited access poses a big challenge particularly for advanced RF architectures where calibration of internal parameters is necessary and ensure proper operation. Therefore low-overhead built-in Self-Test (BIST) solution for advanced RF transceiver is proposed. In this dissertation. Firstly, comprehensive BIST solution for RF polar transceivers using on-chip resources is presented. In the receiver, phase and gain mismatches degrade sensitivity and error vector magnitude (EVM). In the transmitter, delay skew between the envelope and phase signals and the finite envelope bandwidth can create intermodulation distortion (IMD) that leads to violation of spectral mask requirements. Characterization and calibration of these parameters with analytical model would reduce the test time and cost considerably. Hence, a technique to measure and calibrate impairments of the polar transceiver in the loop-back mode is proposed. Secondly, robust amplitude measurement technique for RF BIST application and BIST circuits for loop-back connection are discussed. Test techniques using analytical model are explained and BIST circuits are introduced. Next, a self-compensating built-in self-test solution for RF Phased Array Mismatch is proposed. In the proposed method, a sinusoidal test signal with unknown amplitude is applied to the inputs of two adjacent phased array elements and measure the baseband output signal after down-conversion. Mathematical modeling of the circuit impairments and phased array behavior indicates that by using two distinct input amplitudes, both of which can remain unknown, it is possible to measure the important parameters of the phased array, such as gain and phase mismatch. In addition, proposed BIST system is designed and fabricated using IBM 180nm process and a prototype four-element phased-array PCB is also designed and fabricated for verifying the proposed method. Finally, process independent gain measurement via BIST/DUT co-design is explained. Design methodology how to reduce performance impact significantly is discussed. Simulation and hardware measurements results for the proposed techniques show that the proposed technique can characterize the targeted impairments accurately.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Four-element phased-array beamformers and a self-interference canceling full-duplex transciver in 130-nm SiGe for 5G applications at 26 GHz

This thesis is on the design of radio-frequency (RF) integrated front-end circuits for next generation 5G communication systems. The demand for higher data rates and lower latency in 5G networks can only be met using several new technologies including, but not limited to, mm-waves, massive-MIMO, and full-duplex. Use of mm-waves provides more bandwidth that is necessary for high data rates at the cost of increased attenuation in air. Massive-MIMO arrays are required to compensate for this increased path loss by providing beam steering and array gain. Furthermore, full duplex operation is desirable for improved spectrum efficiency and reduced latency. The difficulty of full duplex operation is the self-interference (SI) between transmit (TX) and receive (RX) paths. Conventional methods to suppress this interference utilize either bulky circulators, isolators, couplers or two separate antennas. These methods are not suitable for fully-integrated full-duplex massive-MIMO arrays. This thesis presents circuit and system level solutions to the issues summarized above, in the form of SiGe integrated circuits for 5G applications at 26 GHz. First, a full-duplex RF front-end architecture is proposed that is scalable to massive-MIMO arrays. It is based on blind, RF self-interference cancellation that is applicable to single/shared antenna front-ends. A high resolution RF vector modulator is developed, which is the key building block that empowers the full-duplex frontend architecture by achieving better than state-of-the-art 10-b monotonic phase control. This vector modulator is combined with linear-in-dB variable gain amplifiers and attenuators to realize a precision self-interference cancellation circuitry. Further, adaptive control of this SI canceler is made possible by including an on-chip low-power IQ downconverter. It correlates copies of transmitted and received signals and provides baseband/dc outputs that can be used to adaptively control the SI canceler. The solution comes at the cost of minimal additional circuitry, yet significantly eases linearity requirements of critical receiver blocks at RF/IF such as mixers and ADCs. Second, to complement the proposed full-duplex front-end architecture and to provide a more complete solution, high-performance beamformer ICs with 5-/6- b phase and 3-/4-b amplitude control capabilities are designed. Single-channel, separate transmitter and receiver beamformers are implemented targeting massive- MIMO mode of operation, and their four-channel versions are developed for phasedarray communication systems. Better than state-of-the-art noise performance is obtained in the RX beamformer channel, with a full-channel noise figure of 3.3 d

System Identification, Diagnosis, and Built-In Self-Test of High Switching Frequency DC-DC Converters

abstract: Complex electronic systems include multiple power domains and drastically varying dynamic power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to smaller solution size (higher power density) and higher efficiency. As the filter components become smaller in value and size, they are unfortunately also subject to higher process variations and worse degradation profiles jeopardizing stable operation of the power supply. This dissertation presents techniques to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation. A digital pseudo-noise (PN) based stimulus is used to excite the DC-DC system at various circuit nodes to calculate the corresponding closed-loop impulse response. The test signal energy is spread over a wide bandwidth and the signal analysis is achieved by correlating the PN input sequence with the disturbed output generated, thereby accumulating the desired behavior over time. A mixed-signal cross-correlation circuit is used to derive on-chip impulse responses, with smaller memory and lower computational requirement in comparison to a digital correlator approach. Model reference based parametric and non-parametric techniques are discussed to analyze the impulse response results in both time and frequency domain. The proposed techniques can extract open-loop phase margin and closed-loop unity-gain frequency within 5.2% and 4.1% error, respectively, for the load current range of 30-200mA. Converter parameters such as natural frequency (ω_n ), quality factor (Q), and center frequency (ω_c ) can be estimated within 3.6%, 4.7%, and 3.8% error respectively, over load inductance of 4.7-10.3µH, and filter capacitance of 200-400nF. A 5-MHz switching frequency, 5-8.125V input voltage range, voltage-mode controlled DC-DC buck converter is designed for the proposed built-in self-test (BIST) analysis. The converter output voltage range is 3.3-5V and the supported maximum load current is 450mA. The peak efficiency of the converter is 87.93%. The proposed converter is fabricated on a 0.6µm 6-layer-metal Silicon-On-Insulator (SOI) technology with a die area of 9mm^2 . The area impact due to the system identification blocks including related I/O structures is 3.8% and they consume 530µA quiescent current during operation.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Wireless wire - ultra-low-power and high-data-rate wireless communication systems

With the rapid development of communication technologies, wireless personal-area communication systems gain momentum and become increasingly important. When the market gets gradually saturated and the technology becomes much more mature, new demands on higher throughput push the wireless communication further into the high-frequency and high-data-rate direction. For example, in the IEEE 802.15.3c standard, a 60-GHz physical layer is specified, which occupies the unlicensed 57 to 64 GHz band and supports gigabit links for applications such as wireless downloading and data streaming. Along with the progress, however, both wireless protocols and physical systems and devices start to become very complex. Due to the limited cut-off frequency of the technology and high parasitic and noise levels at high frequency bands, the power consumption of these systems, especially of the RF front-ends, increases significantly. The reason behind this is that RF performance does not scale with technology at the same rate as digital baseband circuits. Based on the challenges encountered, the wireless-wire system is proposed for the millimeter wave high-data-rate communication. In this system, beamsteering directional communication front-ends are used, which confine the RF power within a narrow beam and increase the level of the equivalent isotropic radiation power by a factor equal to the number of antenna elements. Since extra gain is obtained from the antenna beamsteering, less front-end gain is required, which will reduce the power consumption accordingly. Besides, the narrow beam also reduces the interference level to other nodes. In order to minimize the system average power consumption, an ultra-low power asynchronous duty-cycled wake-up receiver is added to listen to the channel and control the communication modes. The main receiver is switched on by the wake-up receiver only when the communication is identified while in other cases it will always be in sleep mode with virtually no power consumed. Before transmitting the payload, the event-triggered transmitter will send a wake-up beacon to the wake-up receiver. As long as the wake-up beacon is longer than one cycle of the wake-up receiver, it can be captured and identified. Furthermore, by adopting a frequency-sweeping injection locking oscillator, the wake-up receiver is able to achieve good sensitivity, low latency and wide bandwidth simultaneously. In this way, high-data-rate communication can be achieved with ultra-low average power consumption. System power optimization is achieved by optimizing the antenna number, data rate, modulation scheme, transceiver architecture, and transceiver circuitries with regards to particular application scenarios. Cross-layer power optimization is performed as well. In order to verify the most critical elements of this new approach, a W-band injection-locked oscillator and the wake-up receiver have been designed and implemented in standard TSMC 65-nm CMOS technology. It can be seen from the measurement results that the wake-up receiver is able to achieve about -60 dBm sensitivity, 10 mW peak power consumption and 8.5 µs worst-case latency simultaneously. When applying a duty-cycling scheme, the average power of the wake-up receiver becomes lower than 10 µW if the event frequency is 1000 times/day, which matches battery-based or energy harvesting-based wireless applications. A 4-path phased-array main receiver is simulated working with 1 Gbps data rate and on-off-keying modulation. The average power consumption is 10 µW with 10 Gb communication data per day

High-speed optical data transmission for detector instrumentation in particle physics

This work discusses the advantage of optical transmission utilizing wavelength-division multiplexing for the read-out of experimental data in detector instrumentation in high-energy physics, astroparticle physics or photon science. A multi-channel optical transmitter is developed as the core component on a silicon-on-insulator platform. It implements Mach-Zehnder modulators with a depletion-type pn-phase shifter in each arm, while the (de )multiplexers rely on planar concave gratings. The modulator design is expected to support a symbol rate in the range 40 GBd even with a phase shifter length of 3 mm. The development of an efficient simulation method is presented, which allows for the reliable prediction of the steady-state modulator characteristics. Furthermore, this work addresses the packaging technology for grating-coupled silicon photonic components. In particular, a fabrication and assembly process for a planar fiber-to-chip coupling using angle-polished single-mode fibers is developed. A long-term-stable coupling with a small footprint is achieved, of which the coupling efficiency is only weakly dependent on ambient conditions

Millimeter-Wave MMICs and Applications

As device technology improves, interest in the millimeter-wave band grows. Wireless communication systems migrate to higher frequencies, millimeter-wave radars and passive sensors find new solid-state implementations that promise improved performance, and entirely new applications in the millimeter-wave band become feasible. The circuit or system designer is faced with a new and unique set of challenges and constraints to deal with in order to use this portion of the spectrum successfully. In particular, the advantages of monolithic integration become increasingly important. This thesis presents many new developments in Monolithic Millimeter-Wave Integrated Circuits (MMICs), both the chips themselves and systems that use them. It begins with an overview of the various applications of millimeter waves, including a discussion of specific projects that the author is involved in and why many of them demand a MMIC implementation. In the subsequent chapters, new MMIC chips are described in detail, as is the role they play in real-world projects. Multi-chip modules are also presented with specific attention given to the practical details of MMIC packaging and multi-chip integration. The thesis concludes with a summary of the works presented thus far and their overall impact on the field of millimeter-wave engineering.</p

An X-Band power amplifier design for on-chip RADAR applications

Tremendous growth of RAdio Detecting And Ranging (RADAR) and communication electronics require low manufacturing cost, excellent performance, minimum area and highly integrated solutions for transmitter/receiver (T/R) modules, which are one of the most important blocks of RADAR systems. New circuit topologies and process technologies are investigated to fulfill these requirements of next generation RADAR systems. With the recent improvements, Silicon-Germanium Bipolar CMOS technology became a good candidate for recently used III-V technologies, such as GaAs, InP, and GaN, to meet high speed and performance requirements of present RADAR applications. As new process technologies are used, new solutions and circuit architectures have to be provided while taking into account the advantages and disadvantageous of used technologies. In this thesis, a new T/R module system architecture is presented for single/onchip X-Band phased array RADAR applications. On-chip T/R module consists of five blocks; T/R switch, single-pole double-throw (SPDT) switch, low noise amplifier (LNA), power amplifier (PA), and phase shifter. As the main focus of this thesis, a two-stage power amplifier is realized, discussed and measured. Designed in IHP's 0.25 [micrometer] SiGe BiCMOS process technology, the power amplifier operates in Class-A mode to achieve high linearity and presents a measured small-signal gain of 25 dB at 10 GHz. While achieving an output power of 22 dBm, the power amplifier has drain efficiency of 30 % in saturation. The total die area is 1 [square millimeters], including RF and DC pads. To our knowledge, these results are comparable to and/or better than those reported in the literature

Design of SiGe HBT power amplifiers for microwave radar applications

A novel modification to the standard cascode amplifier architecture is presented in SiGe which allows for an optimal separation of gain and breakdown functions through the mixed breakdown cascade architecture, opening the door for moderate power amplifiers in SiGe. Utilizing this technique, a two-stage, high-gain amplifier operating at X-Band is fabricated and measured. The 20 dB of gain per stage represents the highest gain at X-Band at the time of publication. Additionally, a near one Watt power amplifier is designed and fabricated at X-Band, which represents the highest output power in SiGe at X-Band at time of publication. Related to the power amplifier design, thermal considerations are also investigated. The validity of utilizing lumped mutual thermal coupling in SiGe devices is presented. Using this finding, a thermal coupling model and network which are compliant for use with commonly available HBT models and circuit simulators is presented. This model and network is used to thermally optimize SiGe PA cells based upon layout spacing.Ph.D.Committee Member: John Cressler; Committee Member: John Papapolymerou; Committee Member: Joy Laskar; Committee Member: Thomas Morley; Committee Member: William Hun