Development and testing of an FPGA-controlled switched-integrator current amplifier for use in scanning tunnelling microscopy

The scanning tunnelling microscope (STM) is a very powerful analytic tool capable of achieving atomic resolution. Unfortunately, the STM is restricted to samples that are sufficiently conductive to allow adequate tunneling current for feedback control. The amplifier used to measure the tunneling current is the critical limiting component. If the amplifier could be made more sensitive, the STM could be operated at lower tunneling currents allowing lower conductivity samples to be studied. Most amplifiers used in STM employ a resistor feedback design, which become unstable at high gain necessitating a tradeoff between gain and bandwidth. One way to circumvent that stability problem is to use a capacitor feedback design (switched integrator), which does not exhibit the same stability problem. This comes at the expense of added complexity because the output is the integral of the current and needs to be periodically reset. In this project, a switched-integrator current amplifier is constructed and explored. It consisted of an analog switched integrator controlled by a field-programmable-gate-array (FPGA) with a 16-bit analog-to-digital converter and an 18-bit digital-to-analog converter. A viable prototype was created which allowed for the exploration of the gain, phase, and time delay of such systems. This exploration helped further characterize the important design considerations and trade-offs necessary for such a system. A design sequence is proposed that allows for optimal planning based on the desired tunneling current and system bandwidth

The Telecommunications and Data Acquisition Report

Tracking and ground-based navigation; communications, spacecraft-ground; station control and system technology; capabilities for new projects; networks consolidation program; and network sustaining are described

Fault tolerant programmable digital attitude control electronics study

The attitude control electronics mechanization study to develop a fault tolerant autonomous concept for a three axis system is reported. Programmable digital electronics are compared to general purpose digital computers. The requirements, constraints, and tradeoffs are discussed. It is concluded that: (1) general fault tolerance can be achieved relatively economically, (2) recovery times of less than one second can be obtained, (3) the number of faulty behavior patterns must be limited, and (4) adjoined processes are the best indicators of faulty operation

NASA patent abstracts bibliography: A continuing bibliography. Section 1: Abstracts (supplement 30)

Abstracts are provided for 105 patents and patent applications entered into the NASA scientific and technical information system during the period July 1986 through December 1986. Each entry consists of a citation, an abstract, and in most cases, a key illustration selected from the patent or patent application

Efficient FPGA implementation and power modelling of image and signal processing IP cores

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.Field Programmable Gate Arrays (FPGAs) are the technology of choice in a number ofimage and signal processing application areas such as consumer electronics, instrumentation, medical data processing and avionics due to their reasonable energy consumption, high performance, security, low design-turnaround time and reconfigurability. Low power FPGA devices are also emerging as competitive solutions for mobile and thermally constrained platforms. Most computationally intensive image and signal processing algorithms also consume a lot of power leading to a number of issues including reduced mobility, reliability concerns and increased design cost among others. Power dissipation has become one of the most important challenges, particularly for FPGAs. Addressing this problem requires optimisation and awareness at all levels in the design flow. The key achievements of the work presented in this thesis are summarised here. Behavioural level optimisation strategies have been used for implementing matrix product and inner product through the use of mathematical techniques such as Distributed Arithmetic (DA) and its variations including offset binary coding, sparse factorisation and novel vector level transformations. Applications to test the impact of these algorithmic and arithmetic transformations include the fast Hadamard/Walsh transforms and Gaussian mixture models. Complete design space exploration has been performed on these cores, and where appropriate, they have been shown to clearly outperform comparable existing implementations. At the architectural level, strategies such as parallelism, pipelining and systolisation have been successfully applied for the design and optimisation of a number of cores including colour space conversion, finite Radon transform, finite ridgelet transform and circular convolution. A pioneering study into the influence of supply voltage scaling for FPGA based designs, used in conjunction with performance enhancing strategies such as parallelism and pipelining has been performed. Initial results are very promising and indicated significant potential for future research in this area. A key contribution of this work includes the development of a novel high level power macromodelling technique for design space exploration and characterisation of custom IP cores for FPGAs, called Functional Level Power Analysis and Modelling (FLPAM). FLPAM is scalable, platform independent and compares favourably with existing approaches. A hybrid, top-down design flow paradigm integrating FLPAM with commercially available design tools for systematic optimisation of IP cores has also been developed

The deep space network

Deep Space Network progress in flight project support, tracking and data acquisition research and technology, network engineering, hardware and software implementation, and operations is presented

Conversion from linear to circular polarization in FPGA in real time

ABSTRACT Radio astronomical receivers are now expanding their frequency range to cover large (octave) fractional bandwidths for sensitivity and spectral flexibility, which makes the design of good analogue circular polarizers challenging. Better polarization purity requires a flatter phase response over increasingly wide bandwidth, which is most easily achieved with digital techniques. They offer the ability to form circular polarization with perfect polarization purity over arbitrarily wide fractional bandwidths, due to the ease of introducing a perfect quadrature phase shift. In analogue systems the quadrature phase shift is not accurate in the regions away from the design point or frequency. In digital systems on the contrary, it is possible to introduce the exact quadrature phase shift vectorially to each frequency point in the band thus producing a perfect quadrature phase shift throughout the band. Further, the rapid improvements in field programmable gate arrays provide the high processing power, low cost, portability and reconfigurability needed to make practical the implementation of the formation of circular polarization digitally. It will be possible to carry out broadband polarization observations. Circular polarization is used in very long baseline interferometry (VLBI) due to geometrical and stability considerations. VLBI is often used to explore polarization of radio emission, which often occurs due to synchrotron mechanism, Zeeman effect in atoms and molecules, cyclotron radiation and plasma oscillations in the solar atmosphere. Also VLBI finds application in methods like rotation measure synthesis that can be used to find the magnetic field strength and whose multiwavelength observations determine the direction of magnetic field. So a digital circular polarizer would find a considerable application in VLBI systems. Here I explore the performance of a circular polarizer implemented with digital techniques. I designed a digital circular polarizer in which the intermediate frequency signals from a receiver with native linear polarizations were sampled and converted to circular polarization. The frequency-dependent instrumental phase difference and gain scaling factors were determined using an injected noise signal and applied to the two linear polarizations to equalize the transfer characteristics of the two polarization channels. This equalization was performed in 512 frequency channels over a 500 MHz bandwidth. Circular polarization was formed by quadrature phase shifting and summing the equalized linear polarization signals. I obtained polarization purity of -58 dB corresponding to a D-term of 0.0012 over the whole bandwidth. This value of D-term is an upper limit. This technique enables construction of broad-band radio astronomy receivers with native linear polarization to form circular polarization for VLBI

SETI science working group report

This report covers the initial activities and deliberations of a continuing working group asked to assist the SETI Program Office at NASA. Seven chapters present the group's consensus on objectives, strategies, and plans for instrumental R&D and for a microwave search for extraterrestrial in intelligence (SETI) projected for the end of this decade. Thirteen appendixes reflect the views of their individual authors. Included are discussions of the 8-million-channel spectrum analyzer architecture and the proof-of-concept device under development; signal detection, recognition, and identification on-line in the presence of noise and radio interference; the 1-10 GHz sky survey and the 1-3 GHz targeted search envisaged; and the mutual interests of SETI and radio astronomy. The report ends with a selective, annotated SETI reading list of pro and contra SETI publications

Efficient FPGA implementation and power modelling of image and signal processing IP cores

Field Programmable Gate Arrays (FPGAs) are the technology of choice in a number ofimage and signal processing application areas such as consumer electronics, instrumentation, medical data processing and avionics due to their reasonable energy consumption, high performance, security, low design-turnaround time and reconfigurability. Low power FPGA devices are also emerging as competitive solutions for mobile and thermally constrained platforms. Most computationally intensive image and signal processing algorithms also consume a lot of power leading to a number of issues including reduced mobility, reliability concerns and increased design cost among others. Power dissipation has become one of the most important challenges, particularly for FPGAs. Addressing this problem requires optimisation and awareness at all levels in the design flow. The key achievements of the work presented in this thesis are summarised here. Behavioural level optimisation strategies have been used for implementing matrix product and inner product through the use of mathematical techniques such as Distributed Arithmetic (DA) and its variations including offset binary coding, sparse factorisation and novel vector level transformations. Applications to test the impact of these algorithmic and arithmetic transformations include the fast Hadamard/Walsh transforms and Gaussian mixture models. Complete design space exploration has been performed on these cores, and where appropriate, they have been shown to clearly outperform comparable existing implementations. At the architectural level, strategies such as parallelism, pipelining and systolisation have been successfully applied for the design and optimisation of a number of cores including colour space conversion, finite Radon transform, finite ridgelet transform and circular convolution. A pioneering study into the influence of supply voltage scaling for FPGA based designs, used in conjunction with performance enhancing strategies such as parallelism and pipelining has been performed. Initial results are very promising and indicated significant potential for future research in this area. A key contribution of this work includes the development of a novel high level power macromodelling technique for design space exploration and characterisation of custom IP cores for FPGAs, called Functional Level Power Analysis and Modelling (FLPAM). FLPAM is scalable, platform independent and compares favourably with existing approaches. A hybrid, top-down design flow paradigm integrating FLPAM with commercially available design tools for systematic optimisation of IP cores has also been developed.EThOS - Electronic Theses Online ServiceGBUnited Kingdo