3,866 research outputs found
High-resolution microwave frequency dissemination on an 86-km urban optical link
We report the first demonstration of a long-distance ultra stable frequency
dissemination in the microwave range. A 9.15 GHz signal is transferred through
a 86-km urban optical link with a fractional frequency stability of 1.3x10-15
at 1 s integration time and below 10-18 at one day. The optical link phase
noise compensation is performed with a round-trip method. To achieve such a
result we implement light polarisation scrambling and dispersion compensation.
This link outperforms all the previous radiofrequency links and compares well
with recently demonstrated full optical links.Comment: 11 pages, 5 figure
๊ณ ์ ์๋ฆฌ์ผ ๋งํฌ๋ฅผ ์ํ ๊ณ ๋ฆฌ ๋ฐ์ง๊ธฐ๋ฅผ ๊ธฐ๋ฐ์ผ๋ก ํ๋ ์ฃผํ์ ํฉ์ฑ๊ธฐ
ํ์๋
ผ๋ฌธ(๋ฐ์ฌ) -- ์์ธ๋ํ๊ต๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ ๋ณด๊ณตํ๋ถ, 2022. 8. ์ ๋๊ท .In this dissertation, major concerns in the clocking of modern serial links are discussed. As sub-rate, multi-standard architectures are becoming predominant, the conventional clocking methodology seems to necessitate innovation in terms of low-cost implementation. Frequency synthesis with active, inductor-less oscillators replacing LC counterparts are reviewed, and solutions for two major drawbacks are proposed. Each solution is verified by prototype chip design, giving a possibility that the inductor-less oscillator may become a proper candidate for future high-speed serial links.
To mitigate the high flicker noise of a high-frequency ring oscillator (RO), a reference multiplication technique that effectively extends the bandwidth of the following all-digital phase-locked loop (ADPLL) is proposed. The technique avoids any jitter accumulation, generating a clean mid-frequency clock, overall achieving high jitter performance in conjunction with the ADPLL. Timing constraint for the proper reference multiplication is first analyzed to determine the calibration points that may correct the existent phase errors. The weight for each calibration point is updated by the proposed a priori probability-based least-mean-square (LMS) algorithm. To minimize the time required for the calibration, each gain for the weight update is adaptively varied by deducing a posteriori which error source dominates the others. The prototype chip is fabricated in a 40-nm CMOS technology, and its measurement results verify the low-jitter, high-frequency clock generation with fast calibration settling. The presented work achieves an rms jitter of 177/223 fs at 8/16-GHz output, consuming 12.1/17-mW power.
As the second embodiment, an RO-based ADPLL with an analog technique that addresses the high supply sensitivity of the RO is presented. Unlike prior arts, the circuit for the proposed technique does not extort the RO voltage headroom, allowing high-frequency oscillation. Further, the performance given from the technique is robust over process, voltage, and temperature (PVT) variations, avoiding the use of additional calibration hardware. Lastly, a comprehensive analysis of phase noise contribution is conducted for the overall ADPLL, followed by circuit optimizations, to retain the low-jitter output. Implemented in a 40-nm CMOS technology, the frequency synthesizer achieves an rms jitter of 289 fs at 8 GHz output without any injected supply noise. Under a 20-mVrms white supply noise, the ADPLL suppresses supply-noise-induced jitter by -23.8 dB.๋ณธ ๋
ผ๋ฌธ์ ํ๋ ์๋ฆฌ์ผ ๋งํฌ์ ํด๋ฝํน์ ๊ด์ฌ๋๋ ์ฃผ์ํ ๋ฌธ์ ๋ค์ ๋ํ์ฌ ๊ธฐ์ ํ๋ค. ์ค์๋, ๋ค์ค ํ์ค ๊ตฌ์กฐ๋ค์ด ์ฑํ๋๊ณ ์๋ ์ถ์ธ์ ๋ฐ๋ผ, ๊ธฐ์กด์ ํด๋ผํน ๋ฐฉ๋ฒ์ ๋ฎ์ ๋น์ฉ์ ๊ตฌํ์ ๊ด์ ์์ ์๋ก์ด ํ์ ์ ํ์๋ก ํ๋ค. LC ๊ณต์ง๊ธฐ๋ฅผ ๋์ ํ์ฌ ๋ฅ๋ ์์ ๋ฐ์ง๊ธฐ๋ฅผ ์ฌ์ฉํ ์ฃผํ์ ํฉ์ฑ์ ๋ํ์ฌ ์์๋ณด๊ณ , ์ด์ ๋ฐ์ํ๋ ๋๊ฐ์ง ์ฃผ์ ๋ฌธ์ ์ ๊ณผ ๊ฐ๊ฐ์ ๋ํ ํด๊ฒฐ ๋ฐฉ์์ ํ์ํ๋ค. ๊ฐ ์ ์ ๋ฐฉ๋ฒ์ ํ๋กํ ํ์
์นฉ์ ํตํด ๊ทธ ํจ์ฉ์ฑ์ ๊ฒ์ฆํ๊ณ , ์ด์ด์ ๋ฅ๋ ์์ ๋ฐ์ง๊ธฐ๊ฐ ๋ฏธ๋์ ๊ณ ์ ์๋ฆฌ์ผ ๋งํฌ์ ํด๋ฝํน์ ์ฌ์ฉ๋ ๊ฐ๋ฅ์ฑ์ ๋ํด ๊ฒํ ํ๋ค.
์ฒซ๋ฒ์งธ ์์ฐ์ผ๋ก์จ, ๊ณ ์ฃผํ ๊ณ ๋ฆฌ ๋ฐ์ง๊ธฐ์ ๋์ ํ๋ฆฌ์ปค ์ก์์ ์ํ์ํค๊ธฐ ์ํด ๊ธฐ์ค ์ ํธ๋ฅผ ๋ฐฐ์ํํ์ฌ ๋ท๋จ์ ์์ ๊ณ ์ ๋ฃจํ์ ๋์ญํญ์ ํจ๊ณผ์ ์ผ๋ก ๊ทน๋ํ ์ํค๋ ํ๋ก ๊ธฐ์ ์ ์ ์ํ๋ค. ๋ณธ ๊ธฐ์ ์ ์งํฐ๋ฅผ ๋์ ์ํค์ง ์์ผ๋ฉฐ ๋ฐ๋ผ์ ๊นจ๋ํ ์ค๊ฐ ์ฃผํ์ ํด๋ฝ์ ์์ฑ์์ผ ์์ ๊ณ ์ ๋ฃจํ์ ํจ๊ป ๋์ ์ฑ๋ฅ์ ๊ณ ์ฃผํ ํด๋ฝ์ ํฉ์ฑํ๋ค. ๊ธฐ์ค ์ ํธ๋ฅผ ์ฑ๊ณต์ ์ผ๋ก ๋ฐฐ์ํํ๊ธฐ ์ํ ํ์ด๋ฐ ์กฐ๊ฑด๋ค์ ๋จผ์ ๋ถ์ํ์ฌ ํ์ด๋ฐ ์ค๋ฅ๋ฅผ ์ ๊ฑฐํ๊ธฐ ์ํ ๋ฐฉ๋ฒ๋ก ์ ํ์
ํ๋ค. ๊ฐ ๊ต์ ์ค๋์ ์ฐ์ญ์ ํ๋ฅ ์ ๊ธฐ๋ฐ์ผ๋กํ LMS ์๊ณ ๋ฆฌ์ฆ์ ํตํด ๊ฐฑ์ ๋๋๋ก ์ค๊ณ๋๋ค. ๊ต์ ์ ํ์ํ ์๊ฐ์ ์ต์ํ ํ๊ธฐ ์ํ์ฌ, ๊ฐ ๊ต์ ์ด๋์ ํ์ด๋ฐ ์ค๋ฅ ๊ทผ์๋ค์ ํฌ๊ธฐ๋ฅผ ๊ท๋ฉ์ ์ผ๋ก ์ถ๋ก ํ ๊ฐ์ ๋ฐํ์ผ๋ก ์ง์์ ์ผ๋ก ์ ์ด๋๋ค. 40-nm CMOS ๊ณต์ ์ผ๋ก ๊ตฌํ๋ ํ๋กํ ํ์
์นฉ์ ์ธก์ ์ ํตํด ์ ์์, ๊ณ ์ฃผํ ํด๋ฝ์ ๋น ๋ฅธ ๊ต์ ์๊ฐ์์ ํฉ์ฑํด ๋์ ํ์ธํ์๋ค. ์ด๋ 177/223 fs์ rms ์งํฐ๋ฅผ ๊ฐ์ง๋ 8/16 GHz์ ํด๋ฝ์ ์ถ๋ ฅํ๋ค.
๋๋ฒ์งธ ์์ฐ์ผ๋ก์จ, ๊ณ ๋ฆฌ ๋ฐ์ง๊ธฐ์ ๋์ ์ ์ ๋
ธ์ด์ฆ ์์กด์ฑ์ ์ํ์ํค๋ ๊ธฐ์ ์ด ํฌํจ๋ ์ฃผํ์ ํฉ์ฑ๊ธฐ๊ฐ ์ค๊ณ๋์๋ค. ์ด๋ ๊ณ ๋ฆฌ ๋ฐ์ง๊ธฐ์ ์ ์ ํค๋๋ฃธ์ ๋ณด์กดํจ์ผ๋ก์ ๊ณ ์ฃผํ ๋ฐ์ง์ ๊ฐ๋ฅํ๊ฒ ํ๋ค. ๋์๊ฐ, ์ ์ ๋
ธ์ด์ฆ ๊ฐ์ ์ฑ๋ฅ์ ๊ณต์ , ์ ์, ์จ๋ ๋ณ๋์ ๋ํ์ฌ ๋ฏผ๊ฐํ์ง ์์ผ๋ฉฐ, ๋ฐ๋ผ์ ์ถ๊ฐ์ ์ธ ๊ต์ ํ๋ก๋ฅผ ํ์๋ก ํ์ง ์๋๋ค. ๋ง์ง๋ง์ผ๋ก, ์์ ๋
ธ์ด์ฆ์ ๋ํ ํฌ๊ด์ ๋ถ์๊ณผ ํ๋ก ์ต์ ํ๋ฅผ ํตํ์ฌ ์ฃผํ์ ํฉ์ฑ๊ธฐ์ ์ ์ก์ ์ถ๋ ฅ์ ๋ฐฉํดํ์ง ์๋ ๋ฐฉ๋ฒ์ ๊ณ ์ํ์๋ค. ํด๋น ํ๋กํ ํ์
์นฉ์ 40-nm CMOS ๊ณต์ ์ผ๋ก ๊ตฌํ๋์์ผ๋ฉฐ, ์ ์ ๋
ธ์ด์ฆ๊ฐ ์ธ๊ฐ๋์ง ์์ ์ํ์์ 289 fs์ rms ์งํฐ๋ฅผ ๊ฐ์ง๋ 8 GHz์ ํด๋ฝ์ ์ถ๋ ฅํ๋ค. ๋ํ, 20 mVrms์ ์ ์ ๋
ธ์ด์ฆ๊ฐ ์ธ๊ฐ๋์์ ๋์ ์ ๋๋๋ ์งํฐ์ ์์ -23.8 dB ๋งํผ ์ค์ด๋ ๊ฒ์ ํ์ธํ์๋ค.1 Introduction 1
1.1 Motivation 3
1.1.1 Clocking in High-Speed Serial Links 4
1.1.2 Multi-Phase, High-Frequency Clock Conversion 8
1.2 Dissertation Objectives 10
2 RO-Based High-Frequency Synthesis 12
2.1 Phase-Locked Loop Fundamentals 12
2.2 Toward All-Digital Regime 15
2.3 RO Design Challenges 21
2.3.1 Oscillator Phase Noise 21
2.3.2 Challenge 1: High Flicker Noise 23
2.3.3 Challenge 2: High Supply Noise Sensitivity 26
3 Filtering RO Noise 28
3.1 Introduction 28
3.2 Proposed Reference Octupler 34
3.2.1 Delay Constraint 34
3.2.2 Phase Error Calibration 38
3.2.3 Circuit Implementation 51
3.3 IL-ADPLL Implementation 55
3.4 Measurement Results 59
3.5 Summary 63
4 RO Supply Noise Compensation 69
4.1 Introduction 69
4.2 Proposed Analog Closed Loop for Supply Noise Compensation 72
4.2.1 Circuit Implementation 73
4.2.2 Frequency-Domain Analysis 76
4.2.3 Circuit Optimization 81
4.3 ADPLL Implementation 87
4.4 Measurement Results 90
4.5 Summary 98
5 Conclusions 99
A Notes on the 8REF 102
B Notes on the ACSC 105๋ฐ
Process and Temperature Compensated Wideband Injection Locked Frequency Dividers and their Application to Low-Power 2.4-GHz Frequency Synthesizers
There has been a dramatic increase in wireless awareness among the user community in the past five years. The 2.4-GHz Industrial, Scientific and Medical (ISM) band is being used for a diverse range of applications due to the following reasons. It is the only unlicensed band approved worldwide and it offers more bandwidth and supports higher data rates compared to the 915-MHz ISM band. The power consumption of devices utilizing the 2.4-GHz band is much lower compared to the 5.2-GHz ISM band. Protocols like Bluetooth and Zigbee that utilize the 2.4-GHz ISM band are becoming extremely popular.
Bluetooth is an economic wireless solution for short range connectivity between PC, cell phones, PDAs, Laptops etc. The Zigbee protocol is a wireless technology that was developed as an open global standard to address the unique needs of low-cost, lowpower, wireless sensor networks. Wireless sensor networks are becoming ubiquitous, especially after the recent terrorist activities. Sensors are employed in strategic locations for real-time environmental monitoring, where they collect and transmit data frequently to a nearby terminal. The devices operating in this band are usually compact and battery powered. To enhance battery life and avoid the cumbersome task of battery replacement, the devices used should consume extremely low power. Also, to meet the growing demands cost and sized has to be kept low which mandates fully monolithic implementation using low cost process.
CMOS process is extremely attractive for such applications because of its low cost and the possibility to integrate baseband and high frequency circuits on the same chip. A fully integrated solution is attractive for low power consumption as it avoids the need for power hungry drivers for driving off-chip components. The transceiver is often the most power hungry block in a wireless communication system. The frequency divider (prescaler) and the voltage controlled oscillator in the transmitterโs frequency synthesizer are among the major sources of power consumption. There have been a number of publications in the past few decades on low-power high-performance VCOs. Therefore this work focuses on prescalers.
A class of analog frequency dividers called as Injection-Locked Frequency Dividers (ILFD) was introduced in the recent past as low power frequency division. ILFDs can consume an order of magnitude lower power when compared to conventional flip-flop based dividers. However the range of operation frequency also knows as the locking range is limited. ILFDs can be classified as LC based and Ring based. Though LC based are insensitive to process and temperature variation, they cannot be used for the 2.4-GHz ISM band because of the large size of on-chip inductors at these frequencies. This causes a lot of valuable chip area to be wasted. Ring based ILFDs are compact and provide a low power solution but are extremely sensitive to process and temperature variations. Process and temperature variation can cause ring based ILFD to loose lock in the desired operating band.
The goal of this work is to make the ring based ILFDs useful for practical applications. Techniques to extend the locking range of the ILFDs are discussed. A novel and simple compensation technique is devised to compensate the ILFD and keep the locking range tight with process and temperature variations. The proposed ILFD is used in a 2.4-GHz frequency synthesizer that is optimized for fractional-N synthesis. Measurement results supporting the theory are provided
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Noise shaping Asynchronous SAR ADC based time to digital converter
Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin
Integrated radio frequency synthetizers for wireless applications
This thesis consists of six publications and an overview of the research topic, which is also a summary of the work. The research described in this thesis concentrates on the design of phase-locked loop radio frequency synthesizers for wireless applications. In particular, the focus is on the implementation of the prescaler, the phase detector, and the chargepump.
This work reviews the requirements set for the frequency synthesizer by the wireless standards, and how these requirements are derived from the system specifications. These requirements apply to both integer-N and fractional-N synthesizers. The work also introduces the special considerations related to the design of fractional-N phase-locked loops. Finally, implementation alternatives for the different building blocks of the synthesizer are reviewed.
The presented work introduces new topologies for the phase detector and the chargepump, and improved topologies for high speed CMOS prescalers. The experimental results show that the presented topologies can be successfully used in both integer-N and fractional-N synthesizers with state-of-the-art performance.
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The S2 VLBI Correlator: A Correlator for Space VLBI and Geodetic Signal Processing
We describe the design of a correlator system for ground and space-based
VLBI. The correlator contains unique signal processing functions: flexible LO
frequency switching for bandwidth synthesis; 1 ms dump intervals, multi-rate
digital signal-processing techniques to allow correlation of signals at
different sample rates; and a digital filter for very high resolution
cross-power spectra. It also includes autocorrelation, tone extraction, pulsar
gating, signal-statistics accumulation.Comment: 44 pages, 13 figure
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