Graphical microcode simulator with a reconfigurable datapath

Microcode is a symbolic way to simplify control design that allows changing, testing and updating the control unit of processors. By changing the microcode, the same datapath can be used for an entirely different application, such as supporting a completely different instruction set. For these reasons, a majority of control units in modern day processors are microcoded. The object was to investigate and implement a graphical microcode simulator with a reconfigurable datapath and microcode format. By allowing a wide configuration of the datapath, many types of logical processors can be designed and simulated. The resulting implemented simulator is able to fill the void in microprogramming tools since there are no graphical microcode simulators that allow such customization of the datapath. The customization of the datapath goes beyond allowing different files specifying the datapath, it allows the datapath to be created and modified using the graphical interface.This tool is able to be used to design and simulate general-purpose processors and application specific processors through datapath and microcode configurations. In the academic setting, this tool provides easier microcode testing through verification on the instruction level for instructors and provide simulation debugging through code tracing and breakpoints for students

A machine-independent microprogram development system

The aims of this project are twofold. They are firstly, to implement a microprogram development system that allows the programmer to write microcode for any microprogrammable machine, and secondly, to build a microprogrammable machine, incorporating the user friendliness of a simulator, while still providing the 'hands on' experience obtained actual hardware. Microprogram development involves a two stage process. The first step is to describe the target machine, using format descriptions and mnemonic-based template definitions. The second stage involves using the defined mnemonics to write the microcodes for the target machine. This includes an assembly phase to translate the mnemonics into the binary microinstructions. Three main components constitute the microprogrammable machine. The Arithmetic and Logic Unit (ALU) is built using chips from Advanced Micro Devices' Am29ØØ bit-slice family, the action of the Microprogram Control Unit (MCU) is simulated by software running on an IBM Personal Computer, and a section of the IBM PC's main memory acts as the Control Store (CS) for the system. The ALU is built on a prototyping card that plugs into one of the slots on the IBM PC's mother board. A hardware simulator program, that produces the effect of the ALU, has also been developed. A small assembly language has been developed using the system, to test the various functions of the system. A mini-assembler has also been written to facilitate assembly of the above language. A group of honours students at Rhodes University tested the microprogram development system. Their ideas and suggestions have been tabulated in this report and some of them have been used to enhance the system's performance. The concept of allowing 'inline' microinstructions in the macroprogram is also investigated in this report and a method of implementing this is shown

Specifications and programs for computer software validation

Three software products developed during the study are reported and include: (1) FORTRAN Automatic Code Evaluation System, (2) the Specification Language System, and (3) the Array Index Validation System

Behavioral synthesis from VHDL using structured modeling

This dissertation describes work in behavioral synthesis involving the development of a VHDL Synthesis System VSS which accepts a VHDL behavioral input specification and performs technology independent synthesis to generate a circuit netlist of generic components. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization.A Structured Modeling methodology has been developed to suggest standard VHDL modeling practices for synthesis. Structured modeling provides recommendations for the use of available VHDL description styles so that optimal designs will be synthesized.A design composed of generic components is synthesized from the input description through a process of Graph Compilation, Graph Criticism, and Design Compilation. Experiments were performed to demonstrate the effects of different modeling styles on the quality of the design produced by VSS. Several alternative VHDL models were examined for each benchmark, illustrating the improvements in design quality achieved when Structured Modeling guidelines were followed

Advanced software techniques for data management systems. Volume 1: Study of software aspects of the phase B space shuttle avionics system

An overview of the executive system design task is presented. The flight software executive system, software verification, phase B baseline avionics system review, higher order languages and compilers, and computer hardware features are also discussed

ASLP: a list processor for artificial intelligence applications.

by Cheang Sin Man.Thesis (M.Phil.)--Chinese University of Hong Kong, 1990.Bibliography: leaves 137-140.ABSTRACT --- p.iACKNOWLEDGEMENTS --- p.iiTABLE OF CONTENTS --- p.iiiChapter CHAPTER 1 --- INTRODUCTION --- p.1Chapter 1.1 --- Lisp as an AI Programming Language --- p.1Chapter 1.2 --- Assisting List Processing with Hardware --- p.2Chapter 1.3 --- Simulation Study --- p.2Chapter 1.4 --- Implementation --- p.3Chapter 1.4.1 --- Hardware --- p.3Chapter 1.4.2 --- Software --- p.3Chapter 1.5 --- Performance --- p.4Chapter CHAPTER 2 --- LISP AND EXISTING LISP MACHINES --- p.5Chapter 2.1 --- Lisp and its Internal Structure --- p.5Chapter 2.1.1 --- The List Structure in Lisp --- p.5Chapter 2.1.2 --- Data Types in Lisp --- p.7Chapter 2.1.3 --- Lisp Functions --- p.8Chapter 2.1.4 --- Storage Management of Lisp --- p.9Chapter 2.2 --- Existing Lisp Machines --- p.11Chapter 2.2.1 --- Types of AI Architecture --- p.11Language-Based architecture --- p.11Knowledge-Based architecture --- p.12Semantic networks --- p.12Chapter 2.2.2 --- Lisp Machines --- p.12Solving problems of Lisp --- p.13Chapter 2.2.3 --- Classes of Lisp Machines --- p.14Two M Lisp machine examples --- p.15A class P machine example --- p.17A class S machine example --- p.17The best class for Lisp --- p.19Chapter 2.3 --- Execution Time Analysis of a Lisp System --- p.20Chapter 2.3.1 --- CPU Time Statistics --- p.20Chapter 2.3.2 --- Statistics Analysis --- p.24Chapter CHAPTER 3 --- OVERALL ARCHITECTURE OF THE ASLP --- p.27Chapter 3.1 --- An Arithmetical & Symbolical List Processor --- p.27Chapter 3.2 --- Multiple Memory Modules --- p.30Chapter 3.3 --- Large Number of Registers --- p.31Chapter 3.4 --- Multiple Buses --- p.34Chapter 3.5 --- Special Function Units --- p.35Chapter CHAPTER 4 --- PARALLELISM IN THE ASLP --- p.36Chapter 4.1 --- Parallel Data Movement --- p.36Chapter 4.2 --- Wide Memory Modules --- p.37Chapter 4.3 --- Parallel Memory Access --- p.39Chapter 4.3.1 --- Parallelism and Pipelining --- p.39Chapter 4.4 --- Pipelined Micro-Instructions --- p.40Chapter 4.4.1 --- Memory access pipelining --- p.41Chapter 4.5 --- Performance Estimation --- p.44Chapter 4.6 --- Parallel Execution with the Host Computer --- p.45Chapter CHAPTER 5 --- SIMULATION STUDY OF THE ASLP --- p.47Chapter 5.1 --- Why Simulation is needed for the ASLP? --- p.47Chapter 5.2 --- The Structure of the HOCB Simulator --- p.48Chapter 5.2.1 --- Activity-Oriented Simulation for the ASLP --- p.50Chapter 5.3 --- The Hardware Object Declaration Method --- p.50Chapter 5.4 --- A Register-Level Simulation of the ASLP --- p.53Chapter 5.4.1 --- A List Function Simulation --- p.54Chapter CHAPTER 6 --- DESIGN AND IMPLEMENTATION OF THE ASLP --- p.57Chapter 6.1 --- Hardware --- p.57Chapter 6.1.1 --- Microprogrammable Controller --- p.57The instruction cycle of the micro-controller --- p.59Chapter 6.1.2 --- Chip Selection and Allocation --- p.59Chapter 6.2 --- Software --- p.61Chapter 6.2.1 --- Instruction Passing --- p.61Chapter 6.2.2 --- Microprogram Development --- p.62Microprogram field definition --- p.64Micro-assembly language --- p.65Macro-instructions --- p.65Down-loading of Micro-Codes --- p.66Interfacing to C language --- p.66A Turbo C Function Library --- p.67Chapter CHAPTER 7 --- PERFORMANCE EVALUATION OF THE ASLP …… --- p.68Chapter 7.1 --- Micro-Functions in the ASLP --- p.68Chapter 7.2 --- Functions in the C Library --- p.71Chapter CHAPTER 8 --- FUNCTIONAL EVALUATION OF THE ASLP --- p.77Chapter 8.1 --- A Relational Database on the ASLP --- p.77Chapter 8.1.1 --- Data Representation --- p.77Chapter 8.1.2 --- Performance of the Database System --- p.79Chapter 8.2 --- Other Potential Applications --- p.80Chapter CHAPTER 9 --- FUTURE DEVELOPMENT OF THE ASLP --- p.81Chapter 9.1 --- An Expert System Shell on the ASLP --- p.81Chapter 9.1.1 --- Definition of Objects --- p.81Chapter 9.1.2 --- Knowledge Representation --- p.84Chapter 9.1.3 --- Knowledge Representation in the ASLP --- p.85Chapter 9.1.4 --- Overall Structure --- p.88Chapter 9.2 --- Reducing the Physical Size by Employing VLSIs --- p.89Chapter CHAPTER 10 --- CONCLUSION --- p.92Chapter APPENDIX A --- BLOCK DIAGRAM --- p.95Chapter APPENDIX B --- ASLP CIRCUIT DIAGRAMS --- p.97Chapter APPENDIX C --- ASLP PC-BOARD LAYOUTS --- p.114Chapter APPENDIX D --- MICRO-CONTROL SIGNAL ASSIGNMENT --- p.121Chapter APPENDIX E --- MICRO-FIELD DEFINITION --- p.124Chapter APPENDIX F --- MACRO DEFINITION --- p.133Chapter APPENDIX G --- REGISTER ASSIGNMENT --- p.134PUBLICATIONS --- p.136REFERENCES --- p.13

REGTRAN and MICRO, the implementation of two digital system simulators

REGTRAN (REGister TRANsfer), a hardware description language and SYSSIM (SYStems SIMulation), a simulator for the system described by REGTRAN were originally developed by Edward Pett, Jr [33] at the University of Texas at Austin. These two programs are successfully used to simulate many digital systems of complex nature. It is the primary purpose of this paper to describe the implementation of these two programs for KRONOS at Oregon State University. In this process, various problems, due to the differences in the operating systems, were faced. These problems are discussed in detail and the changes that were made are included. REGTRAN and SYSSIM are not capable of simulating micro-instructions or a microprocessor. For this reason, another simulator MICRO is developed. Detailed description of MICRO and its use as a general purpose simulator as well as a microprogram simulator are given in detail. As an example, partial emulation of DEC PDP-8 is shown. Suggestions for the improvement of MICRO, REGTRAN and SYSSIM are mentioned

Measurements, Models, Systems and Design

531 s.

Advanced data management system analysis techniques study

The state of the art of system analysis is reviewed, emphasizing data management. Analytic, hardware, and software techniques are described

An automatic microprogramming system.

by Wu Kam-wah.Bibliography: leaves [129]-[130]Thesis (M.Ph.)--Chinese University of Hong Kong, 198