Formal Analysis of Arithmetic Circuits using Computer Algebra - Verification, Abstraction and Reverse Engineering

Despite a considerable progress in verification and abstraction of random and control logic, advances in formal verification of arithmetic designs have been lagging. This can be attributed mostly to the difficulty in an efficient modeling of arithmetic circuits and datapaths without resorting to computationally expensive Boolean methods, such as Binary Decision Diagrams (BDDs) and Boolean Satisfiability (SAT), that require “bit blasting”, i.e., flattening the design to a bit-level netlist. Approaches that rely on computer algebra and Satisfiability Modulo Theories (SMT) methods are either too abstract to handle the bit-level nature of arithmetic designs or require solving computationally expensive decision or satisfiability problems. The work proposed in this thesis aims at overcoming the limitations of analyzing arithmetic circuits, specifically at the post-synthesized phase. It addresses the verification, abstraction and reverse engineering problems of arithmetic circuits at an algebraic level, treating an arithmetic circuit and its specification as a properly constructed algebraic system. The proposed technique solves these problems by function extraction, i.e., by deriving arithmetic function computed by the circuit from its low-level circuit implementation using computer algebraic rewriting technique. The proposed techniques work on large integer arithmetic circuits and finite field arithmetic circuits, up to 512-bit wide containing millions of logic gates

Digital Serializer Design for a SerDes Chip in 130nm CMOS Technology

The development of this project is derived from the effort of previous generations from the System on Chip Design Specialty Program at ITESO, who have pioneered the creation of a serializer-deserializer device for high-speed communications in CMOS technology, aiming towards a small and efficient device. The design flow and enhancements implemented within the digital serializer module of the SerDes system, consists of an 8b10b encoder followed by a parallel to serial converter that together reaches a maximum frequency of 239 MHz in a typical cmrf8sf (130 nm) technology manufacturing process, implemented with Cadence tools. The rtl and testbench were taken from the work of Efrain Arrambide, adding a register to store the current disparity value, and thus, enhance the code by adding primitive blocks to improve the behavior of the serializer module and the validation process, generating a summary for every run. The system on chip flow is followed by choosing the variables that best fit the design and a layout with no design violations is generated during the physical synthesis. The individual module layouts were completed successfully in terms of behavior and violations, while the integration of the mixed signal device showed errors that were not resolved in time for manufacturing.El desarrollo de este proyecto parte del trabajo realizado por las generaciones anteriores de la especialidad de diseño de circuitos integrados del ITESO, quienes fueron pioneros en la creación de un dispositivo para comunicaciones de alta velocidad en tecnología CMOS, con el objetivo de obtener un producto final pequeño y eficiente. El flujo de diseño y mejoras implementadas al módulo serializador digital del sistema SerDes, el cual consiste en un codificador 8b10b seguido de un convertidor de datos de paralelo a serial, alcanza una frecuencia máxima de 239 MHz al ser fabricado y operado en condiciones típicas con la tecnología cmrf8sf (130 nm), además de ser implementado con las herramientas proveídas por Cadence. El código de descripción de hardware y banco de pruebas fueron tomados originalmente de los entregados por Efrain Arrambide, a lo que se le agregó un registro para almacenar el valor de la disparidad del dato enviado, así como la adición de bloques básicos para mejorar el comportamiento y se simplificó el código Verilog. El proceso de validación fue mejorado de tal manera que se prueban bloques por separado y cada iteración genera un registro de transacciones y un resumen al final con los resultados de manera automática para cada iteración. El flujo del diseño de sistemas en chip fue seguido por completo, eligiendo las variables que mejor se adaptan a la respuesta y especificaciones del sistema, así como buscar que genere ninguna violación en el diseño físico. Los distintos bloques del sistema serializador-deserializador fueron diseñados y verificados con éxito, sin embargo, la integración del sistema de señal mixta no fue completada debido a errores que no se lograron resolver a tiempo para cumplir con la fecha de fabricación.ITESO, A. C.Consejo Nacional de Ciencia y Tecnologí

The Logic of Random Pulses: Stochastic Computing.

Recent developments in the field of electronics have produced nano-scale devices whose operation can only be described in probabilistic terms. In contrast with the conventional deterministic computing that has dominated the digital world for decades, we investigate a fundamentally different technique that is probabilistic by nature, namely, stochastic computing (SC). In SC, numbers are represented by bit-streams of 0's and 1's, in which the probability of seeing a 1 denotes the value of the number. The main benefit of SC is that complicated arithmetic computation can be performed by simple logic circuits. For example, a single (logic) AND gate performs multiplication. The dissertation begins with a comprehensive survey of SC and its applications. We highlight its main challenges, which include long computation time and low accuracy, as well as the lack of general design methods. We then address some of the more important challenges. We introduce a new SC design method, called STRAUSS, that generates efficient SC circuits for arbitrary target functions. We then address the problems arising from correlation among stochastic numbers (SNs). In particular, we show that, contrary to general belief, correlation can sometimes serve as a resource in SC design. We also show that unlike conventional circuits, SC circuits can tolerate high error rates and are hence useful in some new applications that involve nondeterministic behavior in the underlying circuitry. Finally, we show how SC's properties can be exploited in the design of an efficient vision chip that is suitable for retinal implants. In particular, we show that SC circuits can directly operate on signals with neural encoding, which eliminates the need for data conversion.PhDComputer Science and EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/113561/1/alaghi_1.pd

Doctor of Philosophy

dissertationFormal verification of hardware designs has become an essential component of the overall system design flow. The designs are generally modeled as finite state machines, on which property and equivalence checking problems are solved for verification. Reachability analysis forms the core of these techniques. However, increasing size and complexity of the circuits causes the state explosion problem. Abstraction is the key to tackling the scalability challenges. This dissertation presents new techniques for word-level abstraction with applications in sequential design verification. By bundling together k bit-level state-variables into one word-level constraint expression, the state-space is construed as solutions (variety) to a set of polynomial constraints (ideal), modeled over the finite (Galois) field of 2^k elements. Subsequently, techniques from algebraic geometry -- notably, Groebner basis theory and technology -- are researched to perform reachability analysis and verification of sequential circuits. This approach adds a "word-level dimension" to state-space abstraction and verification to make the process more efficient. While algebraic geometry provides powerful abstraction and reasoning capabilities, the algorithms exhibit high computational complexity. In the dissertation, we show that by analyzing the constraints, it is possible to obtain more insights about the polynomial ideals, which can be exploited to overcome the complexity. Using our algorithm design and implementations, we demonstrate how to perform reachability analysis of finite-state machines purely at the word level. Using this concept, we perform scalable verification of sequential arithmetic circuits. As contemporary approaches make use of resolution proofs and unsatisfiable cores for state-space abstraction, we introduce the algebraic geometry analog of unsatisfiable cores, and present algorithms to extract and refine unsatisfiable cores of polynomial ideals. Experiments are performed to demonstrate the efficacy of our approaches

Removing constant‐induced errors in stochastic circuits

Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/163790/1/cdt2bf00226.pd

Synthesis of optimal digital shapers with arbitrary noise using simulated annealing

This paper presents the structure, design and implementation of a new way of determining the optimal shaping in time-domain for spectrometers by means of simulated annealing. The proposed algorithm is able to adjust automatically and in real-time the coefficients for shaping an input signal. A practical prototype was designed, implemented and tested on a PowerPC 405 embedded in a Field Programmable Gate Array (FPGA). Lastly, its performance and capabilities were measured using simulations and a neutron monitor.Ministerio de Ciencia e InnovaciónJunta de Comunidades de Castilla-La Manch