7 research outputs found

    A general technique for deterministic model-cycle-level debugging

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    Efficient use of FPGA resources requires FPGA-based performance models of complex hardware to implement one model cycle, i.e., one time-step of the original synchronous system, in several implementation cycles. Generally implementation cycles have no simple relationship with model cycles, and it is tricky to reconstruct the state of the synchronous system at the model-cycle boundaries if only implementation-cycle-level control and information is provided. A good debugging facility needs to provide: complete control over the functioning of the target design being simulated; fast and easy access to all the significant target design state for both monitoring and modification; and some means of accomplishing deterministic execution when the target design is a multicore processor running a parallel application. Moreover, these features need to be provided in a manner which does not incur substantial resource and performance penalties. In this paper, we present a debugging technique based on the LI-BDN theory. We show how the technique facilitates deterministic model-cycle-level debugging. We used it to build the debugging infrastructure for Arete, which is an FPGA-based cycle-accurate multicore simulator. The resource and performance penalties of our debugging technique are minimal; in Arete the debugging infrastructure has area and performance overheads of 5% and 6%, respectively.IBM Researc

    Extending programs with debug-related features, with application to hardware development

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    The capacity and programmability of reconfigurable hardware such as FPGAs has improved steadily over the years, but they do not readily provide any mechanisms for monitoring or debugging running programs. Such mechanisms need to be written into the program itself. This is done using ad hoc methods and primitive tools when compared to CPU programming. This complicates the programming and debugging of reconfigurable hardware. We introduce Program-hosted Directability (PhD), the extension of programs to interpret direction commands at runtime to enable debugging, monitoring and profiling. Normally in hardware development such features are fixed at compile time. We present a language of directing commands, specify its semantics in terms of a simple controller that is embedded with programs, and implement a prototype for directing network programs running in hardware. We show that this approach affords significant flexibility with low impact on hardware utilisation and performance.This work has received funding from the EPSRC NaaS grant EP/K034723/1, European Union's Horizon 2020 research and innovation programme 2014-2018 under the SSICLOPS (grant agreement No. 644866), the Leverhulme Trust Early Career Fellowship ECF-2016-289 and the Newton Trust

    Validation and verification of the interconnection of hardware intellectual property blocks for FPGA-based packet processing systems

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    As networks become more versatile, the computational requirement for supporting additional functionality increases. The increasing demands of these networks can be met by Field Programmable Gate Arrays (FPGA), which are an increasingly popular technology for implementing packet processing systems. The fine-grained parallelism and density of these devices can be exploited to meet the computational requirements and implement complex systems on a single chip. However, the increasing complexity of FPGA-based systems makes them susceptible to errors and difficult to test and debug. To tackle the complexity of modern designs, system-level languages have been developed to provide abstractions suited to the domain of the target system. Unfortunately, the lack of formality in these languages can give rise to errors that are not caught until late in the design cycle. This thesis presents three techniques for verifying and validating FPGA-based packet processing systems described in a system-level description language. First, a type system is applied to the system description language to detect errors before implementation. Second, system-level transaction monitoring is used to observe high-level events on-chip following implementation. Third, the high-level information embodied in the system description language is exploited to allow the system to be automatically instrumented for on-chip monitoring. This thesis demonstrates that these techniques catch errors which are undetected by traditional verification and validation tools. The locations of faults are specified and errors are caught earlier in the design flow, which saves time by reducing synthesis iterations

    Cycle-accurate modeling of multicore processors on FPGAs

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    Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (pages 169-176).We present a novel modeling methodology which enables the generation of a high-performance, cycle-accurate simulator from a cycle-level specification of the target design. We describe Arete, a full-system multicore processor simulator, developed using our modeling methodology. We provide details on Arete's resource-efficient and high-performance implementation on multiple FPGA platforms, and the architectural experiments performed using it. We present clear evidence that the use of simplified models in architectural studies can lead to wrong conclusions. Through two experiments performed using both cycle-accurate and simplified models, we show that on one hand there are substantial quantitative and qualitative differences in results, and on the other, the results match quite well.by Asif Imtiaz Khan.Ph.D

    Entwurf eingebetteter Systeme: Ausführbare Modelle und Fehlersuche

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    Graphische Modelle können mit Hilfe modellgetriebener Ansätze als Programmiersprachen für eingebettete Systeme genutzt werden. Die Arbeit schließt vorhandene Lücken und liefert einen Beitrag zur Zustandsvisualisierung während der Laufzeit zum Zweck der Fehlersuche in solchen Modellen. Dieser resultiert in der flexiblen Debugging-Architektur ModelScope. Die Leistungsfähigkeit von ModelScope wird durch Anbindung unterschiedlicher Modellierungsparadigmen und Ausführungsplattformen validiert

    An Integrated Debugging Environment for Reprogrammble Hardware Systems

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    berkeley.edu Reprogrammable hardware systems are traditionally very difficult to debug due to their high level of parallelism. In our solution to this problem, features are inserted into the user’s design which allow the system to be monitored and updated at runtime. An assortment of logic is added before synthesis to allow variable buffering, assertion checking, and automatic breakpointing. Low-level clock control and access to off-chip storage is managed by a custom hardware operating system. Through the addition of these features, a system can be debugged directly on the hardware, bypassing simulation and reducing iterations through the design flow

    An integrated debugging environment for reprogrammble hardware systems

    No full text
    Reprogrammable hardware systems are traditionally very difficult to debug due to their high level of parallelism. In our solution to this problem, features are inserted into the user's design which allow the system to be monitored and updated at runtime. An assortment of logic is added before synthesis to allow variable buffering, assertion checking, and automatic breakpointing. Low-level clock control and access to off-chip storage is managed by a custom hardware operating system. Through the addition of these features, a system can be debugged directly on the hardware, bypassing simulation and reducing iterations through the design flow. Copyright 2005 ACM.link_to_subscribed_fulltex
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