An Improved Wideband CMOS Current Driver for Bioimpedance Applications

A wideband, CMOS current driver for bioimpedance measurement applications has been designed employing nonlinear feedback. With the introduction of phase compensation, the circuit is able to operate at frequencies higher than the pole frequency of the output transconductor with minimum phase delay. Moreover, it isolates the poles required for stability from the high frequency characteristics of the output transconductor. The circuit has been simulated in a 0.35-μm CMOS technology and operates from ±2.5 V power supplies. Simulations show that for a 1 mAp-p output current, the phase delay is less than 1° for frequencies up to 3 MHz, rising to 1.5° at 5 MHz. Dual frequency currents to the load are demonstrated

A wideband low-distortion CMOS current driver for tissue impedance analysis

Bioimpedance measurements are performed in a variety of medical applications including cancer detection in tissue. Such applications require wideband (typically 1 MHz) accurate ac current drivers with high output impedance and low distortion. This paper presents an integrated current driver that fulfills these requirements. The circuit uses negative feedback to accurately set the output current amplitude into the load. It was fabricated in a 0.35- μm complementary metal–oxide–semiconductor (CMOS) process technology, occupies a core area of 0.4 mm, and operates from ±2.5-V power supplies. For a maximum output current of 1mA p-p, the measured total harmonic distortion is below 0.1%, and the variability of the output current with respect to the load is below 0.5% up to 800 kHz increasing to 0.86% at 1 MHz. The current driver was tested for the detection of cancer sites from postoperative human colon specimens. The circuit is intended for use in active electrode applications

A wideband low-distortion CMOS current driver for tissue impedance analysis

Bioimpedance measurements are performed in a variety of medical applications including cancer detection in tissue. Such applications require wideband (typically 1 MHz) accurate ac current drivers with high output impedance and low distortion. This paper presents an integrated current driver that fulfills these requirements. The circuit uses negative feedback to accurately set the output current amplitude into the load. It was fabricated in a 0.35- μm complementary metal–oxide–semiconductor (CMOS) process technology, occupies a core area of 0.4 mm, and operates from ±2.5-V power supplies. For a maximum output current of 1mA p-p, the measured total harmonic distortion is below 0.1%, and the variability of the output current with respect to the load is below 0.5% up to 800 kHz increasing to 0.86% at 1 MHz. The current driver was tested for the detection of cancer sites from postoperative human colon specimens. The circuit is intended for use in active electrode applications

A low-power recursive I/Q signal generator and current driver for bioimpedance applications

This brief presents a power-efficient quadrature signal generator and current driver application-specific integrated circuit (ASIC) for bioimpedance measurements in an electrical impedance tomography system for monitoring lung function. The signal generator is realized by a digital recursive signal oscillator with the ability of generating quadrature signals over a wide frequency range. The generated in-phase signal is applied to a current driver. It uses a balanced current-mode feedback architecture that monitors the output current through a feedback loop to minimize common-mode voltage build-up at the injection site. The quadrature signals can be used for I/Q demodulation of the measured bioimpedance. The ASIC was designed in TSMC 65 nm technology occupying an area of 0.21 mm2. The current driver can generate up to 0.7 mA current up to 200 kHz and consumes 2.7 mW power using ±0.8 V supplies

A Non-Linear Feedback Current Driver With Automatic Phase Compensation for Bioimpedance Applications

In a conventional sinewave current driver for electrical impedance spectroscopy, as the frequency is increased the input/output phase delay of the current driver increases due to limited bandwidth. The required maximum phase delays of < 4o mean that operation is limited to about 1/12 of the driver bandwidth. A new phase compensation scheme is presented to reduce the phase delay at higher frequencies and can extend the useful operating frequency range of a current driver. The system is capable of reducing the phase error due to the current driver by an appreciable level so that it can operate much nearer the pole frequency of the driver. An integrated circuit was fabricated in a 0.35 5m CMOS process technology which provides a phase error reduction from 22o to 3o at 3 MHz. Its core occupies a silicon area of 1.2 mm2. It operates from a ±2.5 V power supply and can deliver output currents up to 1.8 mAp-p at 3 MHz

Design of ASIC Based Electrical Impedance Tomography Microendoscopic System for Prostate Cancer Surgical Marginal Assessment

Prostate cancer is the second most common cancer in the United States. It is typically treated by surgically excising the cancerous section of the prostate. Because there is not always a visible distinction between the healthy and cancerous sections, surgery often leaves some cancerous tissue behind. This is referred to as a positive surgical margin and it requires adjuvant treatment with adverse side effects. Electrical impedance tomography (EIT) is a low-cost low-form-factor method that can be used to assess surgical marginal intraoperatively to ensure that no cancerous tissue is left behind. EIT-based surgical margin assessment works on the principle that the electrical properties of cancerous tissue are different from those of healthy tissue. These differences are small at lower frequencies but become more pronounced at frequencies of 1 MHz and higher. Unfortunately, previous EIT solutions for surgical marginal assessment have been limited to operating frequencies of less than 1 MHz. This thesis presents a custom application-specific integrated circuit (ASIC) analog front end for performing EIT with a signal-to-noise ratio of 75 dB up to an operating frequency of 10 MHz. The custom ASIC was integrated into a 16-electrode EIT system for surgical marginal assessment. The entire system was tested on a saline phantom with a 2 mm bead that represented a cancerous lesion. The EIT system produced single-frequency and multi-frequency images showing the presence of the inclusion

Adaptive extreme edge computing for wearable devices

Wearable devices are a fast-growing technology with impact on personal healthcare for both society and economy. Due to the widespread of sensors in pervasive and distributed networks, power consumption, processing speed, and system adaptation are vital in future smart wearable devices. The visioning and forecasting of how to bring computation to the edge in smart sensors have already begun, with an aspiration to provide adaptive extreme edge computing. Here, we provide a holistic view of hardware and theoretical solutions towards smart wearable devices that can provide guidance to research in this pervasive computing era. We propose various solutions for biologically plausible models for continual learning in neuromorphic computing technologies for wearable sensors. To envision this concept, we provide a systematic outline in which prospective low power and low latency scenarios of wearable sensors in neuromorphic platforms are expected. We successively describe vital potential landscapes of neuromorphic processors exploiting complementary metal-oxide semiconductors (CMOS) and emerging memory technologies (e.g. memristive devices). Furthermore, we evaluate the requirements for edge computing within wearable devices in terms of footprint, power consumption, latency, and data size. We additionally investigate the challenges beyond neuromorphic computing hardware, algorithms and devices that could impede enhancement of adaptive edge computing in smart wearable devices