16,880 research outputs found
Limits on Fundamental Limits to Computation
An indispensable part of our lives, computing has also become essential to
industries and governments. Steady improvements in computer hardware have been
supported by periodic doubling of transistor densities in integrated circuits
over the last fifty years. Such Moore scaling now requires increasingly heroic
efforts, stimulating research in alternative hardware and stirring controversy.
To help evaluate emerging technologies and enrich our understanding of
integrated-circuit scaling, we review fundamental limits to computation: in
manufacturing, energy, physical space, design and verification effort, and
algorithms. To outline what is achievable in principle and in practice, we
recall how some limits were circumvented, compare loose and tight limits. We
also point out that engineering difficulties encountered by emerging
technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl
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Automatic synthesis of analog layout : a survey
A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon
Tensor Computation: A New Framework for High-Dimensional Problems in EDA
Many critical EDA problems suffer from the curse of dimensionality, i.e. the
very fast-scaling computational burden produced by large number of parameters
and/or unknown variables. This phenomenon may be caused by multiple spatial or
temporal factors (e.g. 3-D field solvers discretizations and multi-rate circuit
simulation), nonlinearity of devices and circuits, large number of design or
optimization parameters (e.g. full-chip routing/placement and circuit sizing),
or extensive process variations (e.g. variability/reliability analysis and
design for manufacturability). The computational challenges generated by such
high dimensional problems are generally hard to handle efficiently with
traditional EDA core algorithms that are based on matrix and vector
computation. This paper presents "tensor computation" as an alternative general
framework for the development of efficient EDA algorithms and tools. A tensor
is a high-dimensional generalization of a matrix and a vector, and is a natural
choice for both storing and solving efficiently high-dimensional EDA problems.
This paper gives a basic tutorial on tensors, demonstrates some recent examples
of EDA applications (e.g., nonlinear circuit modeling and high-dimensional
uncertainty quantification), and suggests further open EDA problems where the
use of tensor computation could be of advantage.Comment: 14 figures. Accepted by IEEE Trans. CAD of Integrated Circuits and
System
Learning the Designer's Preferences to Drive Evolution
This paper presents the Designer Preference Model, a data-driven solution
that pursues to learn from user generated data in a Quality-Diversity
Mixed-Initiative Co-Creativity (QD MI-CC) tool, with the aims of modelling the
user's design style to better assess the tool's procedurally generated content
with respect to that user's preferences. Through this approach, we aim for
increasing the user's agency over the generated content in a way that neither
stalls the user-tool reciprocal stimuli loop nor fatigues the user with
periodical suggestion handpicking. We describe the details of this novel
solution, as well as its implementation in the MI-CC tool the Evolutionary
Dungeon Designer. We present and discuss our findings out of the initial tests
carried out, spotting the open challenges for this combined line of research
that integrates MI-CC with Procedural Content Generation through Machine
Learning.Comment: 16 pages, Accepted and to appear in proceedings of the 23rd European
Conference on the Applications of Evolutionary and bio-inspired Computation,
EvoApplications 202
Trojans in Early Design Steps—An Emerging Threat
Hardware Trojans inserted by malicious foundries
during integrated circuit manufacturing have received substantial
attention in recent years. In this paper, we focus on a different
type of hardware Trojan threats: attacks in the early steps of
design process. We show that third-party intellectual property
cores and CAD tools constitute realistic attack surfaces and that
even system specification can be targeted by adversaries. We
discuss the devastating damage potential of such attacks, the
applicable countermeasures against them and their deficiencies
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Silicon compilation
Silicon compilation is a term used for many different purposes. In this paper we define silicon compilation as a mapping from some higher level description into layout. We define the basic issues in structural and behavioral silicon compilation and some possible solutions to those issues. Finally, we define the concept of an intelligent silicon compiler in which the compiler evaluates the quality of the generated design and attempts to improve it if it is not satisfactory
An efficient nonlinear circuit simulation technique
This paper proposes a novel method for the analysis and simulation of integrated circuits (ICs) with the potential to greatly shorten the IC design cycle. The circuits are assumed to be subjected to input signals that have widely separated rates of variation, e.g., in communication systems, an RF carrier modulated by a low-frequency information signal. The proposed technique involves two stages. Initially, a particular order result for the circuit response is obtained using a multiresolution collocation scheme involving cubic spline wavelet decomposition. A more accurate solution is then obtained by adding another layer to the wavelet series approximation. However, the novel technique presented here enables the reuse of results acquired in the first stage to obtain the second-stage result. Therefore, vast gains in efficiency are obtained. Furthermore, a nonlinear model-order reduction technique can readily be used in both stages making the calculations even more efficient. Results will highlight the efficacy of the proposed approac
MIDAS: Automated Approach to Design Microwave Integrated Inductors and Transformers on Silicon
The design of modern radiofrequency integrated circuits on silicon operating at microwave and millimeter-waves requires the integration of several spiral inductors and transformers that are not commonly available in the process design-kits of the technologies. In this work we present an auxiliary CAD tool for Microwave Inductor (and transformer) Design Automation on Silicon (MIDAS) that exploits commercial simulators and allows the implementation of an automatic design flow, including three-dimensional layout editing and electromagnetic simulations. In detail, MIDAS allows the designer to derive a preliminary sizing of the inductor (transformer) on the bases of the design entries (specifications). It draws the inductor (transformer) layers for the specific process design kit, including vias and underpasses, with or without patterned ground shield, and launches the electromagnetic simulations, achieving effective design automation with respect to the traditional design flow for RFICs. With the present software suite the complete design time is reduced significantly (typically 1 hour on a PC based on Intel® Pentium® Dual 1.80GHz CPU with 2-GB RAM). Afterwards both the device equivalent circuit and the layout are ready to be imported in the Cadence environment
Stochastic Testing Simulator for Integrated Circuits and MEMS: Hierarchical and Sparse Techniques
Process variations are a major concern in today's chip design since they can
significantly degrade chip performance. To predict such degradation, existing
circuit and MEMS simulators rely on Monte Carlo algorithms, which are typically
too slow. Therefore, novel fast stochastic simulators are highly desired. This
paper first reviews our recently developed stochastic testing simulator that
can achieve speedup factors of hundreds to thousands over Monte Carlo. Then, we
develop a fast hierarchical stochastic spectral simulator to simulate a complex
circuit or system consisting of several blocks. We further present a fast
simulation approach based on anchored ANOVA (analysis of variance) for some
design problems with many process variations. This approach can reduce the
simulation cost and can identify which variation sources have strong impacts on
the circuit's performance. The simulation results of some circuit and MEMS
examples are reported to show the effectiveness of our simulatorComment: Accepted to IEEE Custom Integrated Circuits Conference in June 2014.
arXiv admin note: text overlap with arXiv:1407.302
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