Neuroplastic Changes Following Brain Ischemia and their Contribution to Stroke Recovery: Novel Approaches in Neurorehabilitation

Ischemic damage to the brain triggers substantial reorganization of spared areas and pathways, which is associated with limited, spontaneous restoration of function. A better understanding of this plastic remodeling is crucial to develop more effective strategies for stroke rehabilitation. In this review article, we discuss advances in the comprehension of post-stroke network reorganization in patients and animal models. We first focus on rodent studies that have shed light on the mechanisms underlying neuronal remodeling in the perilesional area and contralesional hemisphere after motor cortex infarcts. Analysis of electrophysiological data has demonstrated brain-wide alterations in functional connectivity in both hemispheres, well beyond the infarcted area. We then illustrate the potential use of non-invasive brain stimulation (NIBS) techniques to boost recovery. We finally discuss rehabilitative protocols based on robotic devices as a tool to promote endogenous plasticity and functional restoration

Autonomously Reconfigurable Artificial Neural Network on a Chip

Artificial neural network (ANN), an established bio-inspired computing paradigm, has proved very effective in a variety of real-world problems and particularly useful for various emerging biomedical applications using specialized ANN hardware. Unfortunately, these ANN-based systems are increasingly vulnerable to both transient and permanent faults due to unrelenting advances in CMOS technology scaling, which sometimes can be catastrophic. The considerable resource and energy consumption and the lack of dynamic adaptability make conventional fault-tolerant techniques unsuitable for future portable medical solutions. Inspired by the self-healing and self-recovery mechanisms of human nervous system, this research seeks to address reliability issues of ANN-based hardware by proposing an Autonomously Reconfigurable Artificial Neural Network (ARANN) architectural framework. Leveraging the homogeneous structural characteristics of neural networks, ARANN is capable of adapting its structures and operations, both algorithmically and microarchitecturally, to react to unexpected neuron failures. Specifically, we propose three key techniques --- Distributed ANN, Decoupled Virtual-to-Physical Neuron Mapping, and Dual-Layer Synchronization --- to achieve cost-effective structural adaptation and ensure accurate system recovery. Moreover, an ARANN-enabled self-optimizing workflow is presented to adaptively explore a "Pareto-optimal" neural network structure for a given application, on the fly. Implemented and demonstrated on a Virtex-5 FPGA, ARANN can cover and adapt 93% chip area (neurons) with less than 1% chip overhead and O(n) reconfiguration latency. A detailed performance analysis has been completed based on various recovery scenarios

Long-term stability of the hippocampal neural code as a substrate for episodic memory

The hippocampus supports the initial formation and recall of episodic memories, as well as the consolidation of short-term into long-term memories. The ability of hippocampal neurons to rapidly change their connection strengths during learning and maintain these changes over long time-scales may provide a mechanism supporting memory. However, little evidence currently exists concerning the long-term stability of information contained in hippocampal neuronal activity, likely due to limitations in recording extracellular activity in vivo from the same neurons across days. In this thesis I employ calcium imaging in freely moving mice to longitudinally track the activity of large ensembles of hippocampal neurons. Using this technology, I explore the proposal that long-term stability of hippocampal information provides a substrate for episodic memory in three different ways. First, I tested the hypothesis that hippocampal activity should remain stable across days in the absence of learning. I found that place cells – hippocampal neurons containing information about a mouse’s position – maintain a coherent map relative to each other across long time-scales but exhibit instability in how they anchor to the external world. Furthermore, I found that coherent maps were frequently used to represent a different environment and incorporated learning via changes in a subset of neurons. Next, I examined how learning a spatial alternation task impacts neuron stability. I found that splitter neurons whose activity patterns reflected an animal’s future or past trajectory emerged relatively slowly when compared to place cells. However, splitter neurons remained more consistently active and relayed more consistent spatial information across days than did place cells, suggesting that the utility of information provided by a neuron influences its long term stability. Last, I investigated how protein synthesis, known to be necessary for long-term maintenance of changes in hippocampal neuron connection strengths and for proper memory consolidation, influences their activity patterns across days. I found that along with blocking memory consolidation, inhibiting protein synthesis induced a profound, long-lasting decrease in neuronal activity up to two days later. These results combined demonstrate the importance of rapid, lasting changes in the hippocampal neuronal code to supporting long-term memory

IST Austria Thesis

Brain function is mediated by complex dynamical interactions between excitatory and inhibitory cell types. The Cholecystokinin-expressing inhibitory cells (CCK-interneurons) are one of the least studied types, despite being suspected to play important roles in cognitive processes. We studied the network effects of optogenetic silencing of CCK-interneurons in the CA1 hippocampal area during exploration and sleep states. The cell firing pattern in response to light pulses allowed us to classify the recorded neurons in 5 classes, including disinhibited and non-responsive pyramidal cell and interneurons, and the inhibited interneurons corresponding to the CCK group. The light application, which inhibited the activity of CCK interneurons triggered wider changes in the firing dynamics of cells. We observed rate changes (i.e. remapping) of pyramidal cells during the exploration session in which the light was applied relative to the previous control session that was not restricted neither in time nor space to the light delivery. Also, the disinhibited pyramidal cells had higher increase in bursting than in single spike firing rate as a result of CCK silencing. In addition, the firing activity patterns during exploratory periods were more weakly reactivated in sleep for those periods in which CCK-interneuron were silenced than in the unaffected periods. Furthermore, light pulses during sleep disrupted the reactivation of recent waking patterns. Hence, silencing CCK neurons during exploration suppressed the reactivation of waking firing patterns in sleep and CCK interneuron activity was also required during sleep for the normal reactivation of waking patterns. These findings demonstrate the involvement of CCK cells in reactivation-related memory consolidation. An important part of our analysis was to test the relationship of the identified CCKinterneurons to brain oscillations. Our findings showed that these cells exhibited different oscillatory behaviour during anaesthesia and natural waking and sleep conditions. We showed that: 1) Contrary to the past studies performed under anaesthesia, the identified CCKinterneurons fired on the descending portion of the theta phase in waking exploration. 2) CCKinterneuron preferred phases around the trough of gamma oscillations. 3) Contrary to anaesthesia conditions, the average firing rate of the CCK-interneurons increased around the peak activity of the sharp-wave ripple (SWR) events in natural sleep, which is congruent with new reports about their functional connectivity. We also found that light driven CCK-interneuron silencing altered the dynamics on the CA1 network oscillatory activity: 1) Pyramidal cells negatively shifted their preferred theta phases when the light was applied, while interneurons responses were less consistent. 2) As a population, pyramidal cells negatively shifted their preferred activity during gamma oscillations, albeit we did not find gamma modulation differences related to the light application when pyramidal cells were subdivided into the disinhibited and unaffected groups. 3) During the peak of SWR events, all but the CCK-interneurons had a reduction in their relative firing rate change during the light application as compared to the change observed at SWR initiation. Finally, regarding to the place field activity of the recorded pyramidal neurons, we showed that the disinhibited pyramidal cells had reduced place field similarity, coherence and spatial information, but only during the light application. The mechanisms behind such observed behaviours might involve eCB signalling and plastic changes in CCK-interneuron synapses. In conclusion, the observed changes related to the light-mediated silencing of CCKinterneurons have unravelled characteristics of this interneuron subpopulation that might change the understanding not only of their particular network interactions, but also of the current theories about the emergence of certain cognitive processes such as place coding needed for navigation or hippocampus-dependent memory consolidation

Review of Fault Mitigation Approaches for Deep Neural Networks for Computer Vision in Autonomous Driving

The aim of this work is to identify and present challenges and risks related to the employment of DNNs in Computer Vision for Autonomous Driving. Nowadays one of the major technological challenges is to choose the right technology among the abundance that is available on the market. Specifically, in this thesis it is collected a synopsis of the state-of-the-art architectures, techniques and methodologies adopted for building fault-tolerant hardware and ensuring robustness in DNNs-based Computer Vision applications for Autonomous Driving

Expanding the role of functional mri in rehabilitation research

Functional magnetic resonance imaging (fMRI) based on blood oxygenation level dependent (BOLD) contrast has become a universal methodology in functional neuroimaging. However, the BOLD signal consists of a mix of physiological parameters and has relatively poor reproducibility. As fMRI becomes a prominent research tool for rehabilitation studies involving repeated measures of the human brain, more quantitative and stable fMRI contrasts are needed. This dissertation enhances quantitative measures to complement BOLD fMRI. These additional markers, cerebral blood flow (CBF) and cerebral blood volume (CBV) (and hence cerebral metabolic rate of oxygen (CMRO₂) modeling) are more specific imaging markers of neuronal activity than BOLD. The first aim of this dissertation assesses feasibility of complementing BOLD with quantitative fMRI measures in subjects with central visual impairment. Second, image acquisition and analysis are developed to enhance quantitative fMRI by quantifying CBV while simultaneously acquiring CBF and BOLD images. This aim seeks to relax assumptions related to existing methods that are not suitable for patient populations. Finally, CBF acquisition using a low-cost local labeling coil, which improves image quality, is combined with simultaneous acquisition of two types of traditional BOLD contrast. The demonstrated enhancement of CBF, CBV and CMRO₂measures can lead to better characterization of pathophysiology and treatment effects.Ph.D.Committee Chair: Hu, Xiaoping; Committee Member: Benkeser, Paul; Committee Member: Keilholz, Shella; Committee Member: Sathian, Krish; Committee Member: Schuchard, Ronal

Embedded computing systems design: architectural and application perspectives

Questo elaborato affronta varie problematiche legate alla progettazione e all'implementazione dei moderni sistemi embedded di computing, ponendo in rilevo, e talvolta in contrapposizione, le sfide che emergono all'avanzare della tecnologia ed i requisiti che invece emergono a livello applicativo, derivanti dalle necessità degli utenti finali e dai trend di mercato. La discussione sarà articolata tenendo conto di due punti di vista: la progettazione hardware e la loro applicazione a livello di sistema. A livello hardware saranno affrontati nel dettaglio i problemi di interconnettività on-chip. Aspetto che riguarda la parallelizzazione del calcolo, ma anche l'integrazione di funzionalità eterogenee. Sarà quindi discussa un'architettura d'interconnessione denominata Network-on-Chip (NoC). La soluzione proposta è in grado di supportare funzionalità avanzate di networking direttamente in hardware, consentendo tuttavia di raggiungere sempre un compromesso ottimale tra prestazioni in termini di traffico e requisiti di implementazioni a seconda dell'applicazione specifica. Nella discussione di questa tematica, verrà posto l'accento sul problema della configurabilità dei blocchi che compongono una NoC. Quello della configurabilità, è un problema sempre più sentito nella progettazione dei sistemi complessi, nei quali si cerca di sviluppare delle funzionalità, anche molto evolute, ma che siano semplicemente riutilizzabili. A tale scopo sarà introdotta una nuova metodologia, denominata Metacoding che consiste nell'astrarre i problemi di configurabilità attraverso linguaggi di programmazione di alto livello. Sulla base del metacoding verrà anche proposto un flusso di design automatico in grado di semplificare la progettazione e la configurazione di una NoC da parte del designer di rete. Come anticipato, la discussione si sposterà poi a livello di sistema, per affrontare la progettazione di tali sistemi dal punto di vista applicativo, focalizzando l'attenzione in particolare sulle applicazioni di monitoraggio remoto. A tal riguardo saranno studiati nel dettaglio tutti gli aspetti che riguardano la progettazione di un sistema per il monitoraggio di pazienti affetti da scompenso cardiaco cronico. Si partirà dalla definizione dei requisiti, che, come spesso accade a questo livello, derivano principalmente dai bisogni dell'utente finale, nel nostro caso medici e pazienti. Verranno discusse le problematiche di acquisizione, elaborazione e gestione delle misure. Il sistema proposto introduce vari aspetti innovativi tra i quali il concetto di protocollo operativo e l'elevata interoperabilità offerta. In ultima analisi, verranno riportati i risultati relativi alla sperimentazione del sistema implementato. Infine, il tema del monitoraggio remoto sarà concluso con lo studio delle reti di distribuzione elettrica intelligenti: le Smart Grid, cercando di fare uno studio dello stato dell'arte del settore, proponendo un'architettura di Home Area Network (HAN) e suggerendone una possibile implementazione attraverso Commercial Off the Shelf (COTS)

상변화 메모리 시스템의 간섭 오류 완화 및 RMW 성능 향상 기법

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2021.8. 이혁재.Phase-change memory (PCM) announces the beginning of the new era of memory systems, owing to attractive characteristics. Many memory product manufacturers (e.g., Intel, SK Hynix, and Samsung) are developing related products. PCM can be applied to various circumstances; it is not simply limited to an extra-scale database. For example, PCM has a low standby power due to its non-volatility; hence, computation-intensive applications or mobile applications (i.e., long memory idle time) are suitable to run on PCM-based computing systems. Despite these fascinating features of PCM, PCM is still far from the general commercial market due to low reliability and long latency problems. In particular, low reliability is a painful problem for PCM in past decades. As the semiconductor process technology rapidly scales down over the years, DRAM reaches 10 nm class process technology. In addition, it is reported that the write disturbance error (WDE) would be a serious issue for PCM if it scales down below 54 nm class process technology. Therefore, addressing the problem of WDEs becomes essential to make PCM competitive to DRAM. To overcome this problem, this dissertation proposes a novel approach that can restore meta-stable cells on demand by levering two-level SRAM-based tables, thereby significantly reducing the number WDEs. Furthermore, a novel randomized approach is proposed to implement a replacement policy that originally requires hundreds of read ports on SRAM. The second problem of PCM is a long-latency compared to that of DRAM. In particular, PCM tries to enhance its throughput by adopting a larger transaction unit; however, the different unit size from the general-purpose processor cache line further degrades the system performance due to the introduction of a read-modify-write (RMW) module. Since there has never been any research related to RMW in a PCM-based memory system, this dissertation proposes a novel architecture to enhance the overall system performance and reliability of a PCM-based memory system having an RMW module. The proposed architecture enhances data re-usability without introducing extra storage resources. Furthermore, a novel operation that merges commands regardless of command types is proposed to enhance performance notably. Another problem is the absence of a full simulation platform for PCM. While the announced features of the PCM-related product (i.e., Intel Optane) are scarce due to confidential issues, all priceless information can be integrated to develop an architecture simulator that resembles the available product. To this end, this dissertation tries to scrape up all available features of modules in a PCM controller and implement a dedicated simulator for future research purposes.상변화 메모리는(PCM) 매력적인 특성을 통해 메모리 시스템의 새로운 시대의 시작을 알렸다. 많은 메모리 관련 제품 제조업체(예 : 인텔, SK 하이닉스, 삼성)가 관련 제품 개발에 박차를 가하고 있다. PCM은 단순히 대규모 데이터베이스에만 국한되지 않고 다양한 상황에 적용될 수 있다. 예를 들어, PCM은 비휘발성으로 인해 대기 전력이 낮다. 따라서 계산 집약적인 애플리케이션 또는 모바일 애플리케이션은(즉, 긴 메모리 유휴 시간) PCM 기반 컴퓨팅 시스템에서 실행하기에 적합하다. PCM의 이러한 매력적인 특성에도 불구하고 PCM은 낮은 신뢰성과 긴 대기 시간으로 인해 여전히 일반 산업 시장에서는 DRAM과 다소 격차가 있다. 특히 낮은 신뢰성은 지난 수십 년 동안 PCM 기술의 발전을 저해하는 문제다. 반도체 공정 기술이 수년에 걸쳐 빠르게 축소됨에 따라 DRAM은 10nm 급 공정 기술에 도달하였다. 이어서, 쓰기 방해 오류 (WDE)가 54nm 등급 프로세스 기술 아래로 축소되면 PCM에 심각한 문제가 될 것으로 보고되었다. 따라서, WDE 문제를 해결하는 것은 PCM이 DRAM과 동등한 경쟁력을 갖추도록 하는 데 있어 필수적이다. 이 문제를 극복하기 위해 이 논문에서는 2-레벨 SRAM 기반 테이블을 활용하여 WDE 수를 크게 줄여 필요에 따라 준 안정 셀을 복원할 수 있는 새로운 접근 방식을 제안한다. 또한, 원래 SRAM에서 수백 개의 읽기 포트가 필요한 대체 정책을 구현하기 위해 새로운 랜덤 기반의 기법을 제안한다. PCM의 두 번째 문제는 DRAM에 비해 지연 시간이 길다는 것이다. 특히 PCM은 더 큰 트랜잭션 단위를 채택하여 단위시간 당 데이터 처리량 향상을 도모한다. 그러나 범용 프로세서 캐시 라인과 다른 유닛 크기는 읽기-수정-쓰기 (RMW) 모듈의 도입으로 인해 시스템 성능을 저하하게 된다. PCM 기반 메모리 시스템에서 RMW 관련 연구가 없었기 때문에 본 논문은 RMW 모듈을 탑재 한 PCM 기반 메모리 시스템의 전반적인 시스템 성능과 신뢰성을 향상하게 시킬 수 있는 새로운 아키텍처를 제안한다. 제안된 아키텍처는 추가 스토리지 리소스를 도입하지 않고도 데이터 재사용성을 향상시킨다. 또한, 성능 향상을 위해 명령 유형과 관계없이 명령을 병합하는 새로운 작업을 제안한다. 또 다른 문제는 PCM을 위한 완전한 시뮬레이션 플랫폼이 부재하다는 것이다. PCM 관련 제품(예 : Intel Optane)에 대해 발표된 정보는 대외비 문제로 인해 부족하다. 하지만 알려져 있는 정보를 적절히 취합하면 시중 제품과 유사한 아키텍처 시뮬레이터를 개발할 수 있다. 이를 위해 본 논문은 PCM 메모리 컨트롤러에 필요한 모든 모듈 정보를 활용하여 향후 이와 관련된 연구에서 충분히 사용 가능한 전용 시뮬레이터를 구현하였다.1 INTRODUCTION 1 1.1 Limitation of Traditional Main Memory Systems 1 1.2 Phase-Change Memory as Main Memory 3 1.2.1 Opportunities of PCM-based System 3 1.2.2 Challenges of PCM-based System 4 1.3 Dissertation Overview 7 2 BACKGROUND AND PREVIOUS WORK 8 2.1 Phase-Change Memory 8 2.2 Mitigation Schemes for Write Disturbance Errors 10 2.2.1 Write Disturbance Errors 10 2.2.2 Verification and Correction 12 2.2.3 Lazy Correction 13 2.2.4 Data Encoding-based Schemes 14 2.2.5 Sparse-Insertion Write Cache 16 2.3 Performance Enhancement for Read-Modify-Write 17 2.3.1 Traditional Read-Modify-Write 17 2.3.2 Write Coalescing for RMW 19 2.4 Architecture Simulators for PCM 21 2.4.1 NVMain 21 2.4.2 Ramulator 22 2.4.3 DRAMsim3 22 3 IN-MODULE DISTURBANCE BARRIER 24 3.1 Motivation 25 3.2 IMDB: In Module-Disturbance Barrier 29 3.2.1 Architectural Overview 29 3.2.2 Implementation of Data Structures 30 3.2.3 Modification of Media Controller 36 3.3 Replacement Policy 38 3.3.1 Replacement Policy for IMDB 38 3.3.2 Approximate Lowest Number Estimator 40 3.4 Putting All Together: Case Studies 43 3.5 Evaluation 45 3.5.1 Configuration 45 3.5.2 Architectural Exploration 47 3.5.3 Effectiveness of the Replacement Policy 48 3.5.4 Sensitivity to Main Table Configuration 49 3.5.5 Sensitivity to Barrier Buffer Size 51 3.5.6 Sensitivity to AppLE Group Size 52 3.5.7 Comparison with Other Studies 54 3.6 Discussion 59 3.7 Summary 63 4 INTEGRATION OF AN RMW MODULE IN A PCM-BASED SYSTEM 64 4.1 Motivation 65 4.2 Utilization of DRAM Cache for RMW 67 4.2.1 Architectural Design 67 4.2.2 Algorithm 70 4.3 Typeless Command Merging 73 4.3.1 Architectural Design 73 4.3.2 Algorithm 74 4.4 An Alternative Implementation: SRC-RMW 78 4.4.1 Implementation of SRC-RMW 78 4.4.2 Design Constraint 80 4.5 Case Study 82 4.6 Evaluation 85 4.6.1 Configuration 85 4.6.2 Speedup 88 4.6.3 Read Reliability 91 4.6.4 Energy Consumption: Selecting a Proper Page Size 93 4.6.5 Comparison with Other Studies 95 4.7 Discussion 97 4.8 Summary 99 5 AN ALL-INCLUSIVE SIMULATOR FOR A PCM CONTROLLER 100 5.1 Motivation 101 5.2 PCMCsim: PCM Controller Simulator 103 5.2.1 Architectural Overview 103 5.2.2 Underlying Classes of PCMCsim 104 5.2.3 Implementation of Contention Behavior 108 5.2.4 Modules of PCMCsim 109 5.3 Evaluation 116 5.3.1 Correctness of the Simulator 116 5.3.2 Comparison with Other Simulators 117 5.4 Summary 119 6 Conclusion 120 Abstract (In Korean) 141 Acknowledgment 143박