21 research outputs found
Analyse pire cas exact du réseau AFDX
L'objectif principal de cette thĂšse est de proposer les mĂ©thodes permettant d'obtenir le dĂ©lai de transmission de bout en bout pire cas exact d'un rĂ©seau AFDX. Actuellement, seules des bornes supĂ©rieures pessimistes peuvent ĂȘtre calculĂ©es en utilisant les approches de type Calcul RĂ©seau ou par Trajectoires. Pour cet objectif, diffĂ©rentes approches et outils existent et ont Ă©tĂ© analysĂ©es dans le contexte de cette thĂšse. Cette analyse a mis en Ă©vidence le besoin de nouvelles approches. Dans un premier temps, la vĂ©rification de modĂšle a Ă©tĂ© explorĂ©e. Les automates temporisĂ©s et les outils de verification ayant fait leur preuve dans le domaine temps rĂ©el ont Ă©tĂ© utilisĂ©s. Ensuite, une technique de simulation exhaustive a Ă©tĂ© utilisĂ©e pour obtenir les dĂ©lais de communication pire cas exacts. Pour ce faire, des mĂ©thodes de rĂ©duction de sĂ©quences ont Ă©tĂ© dĂ©finies et un outil a Ă©tĂ© dĂ©veloppĂ©. Ces mĂ©thodes ont Ă©tĂ© appliquĂ©es Ă une configuration rĂ©elle du rĂ©seau AFDX, nous permettant ainsi de valider notre travail sur une configuration de taille industrielle du rĂ©seau AFDX telle que celle embarquĂ©e Ă bord des avions Airbus A380. The main objective of this thesis is to provide methodologies for finding exact worst case end to end communication delays of AFDX network. Presently, only pessimistic upper bounds of these delays can be calculated by using Network Calculus and Trajectory approach. To achieve this goal, different existing tools and approaches have been analyzed in the context of this thesis. Based on this analysis, it is deemed necessary to develop new approaches and algorithms. First, Model checking with existing well established real time model checking tools are explored, using timed automata. Then, exhaustive simulation technique is used with newly developed algorithms and their software implementation in order to find exact worst case communication delays of AFDX network. All this research work has been applied on real life implementation of AFDX network, allowing us to validate our research work on industrial scale configuration of AFDX network such as used on Airbus A380 aircraft. ABSTRACT : The main objective of this thesis is to provide methodologies for finding exact worst case end to end communication delays of AFDX network. Presently, only pessimistic upper bounds of these delays can be calculated by using Network Calculus and Trajectory approach. To achieve this goal, different existing tools and approaches have been analyzed in the context of this thesis. Based on this analysis, it is deemed necessary to develop new approaches and algorithms. First, Model checking with existing well established real time model checking tools are explored, using timed automata. Then, exhaustive simulation technique is used with newly developed algorithms and their software implementation in order to find exact worst case communication delays of AFDX network. All this research work has been applied on real life implementation of AFDX network, allowing us to validate our research work on industrial scale configuration of AFDX network such as used on Airbus A380 aircraft
Computing the exact worst-case End-to-end delays in a Spacewire network using Timed Automata
National audienceSpacewire is a real-time communication network for use onboard satellites. It has been designed to transmit both payload and control/command data. To guarantee that communications respect the real-time constraints, designers use tools to compute the worst-case end-to-end delays. Among these tools, recursive flow analysis and Network Calculus approaches have been studied. This paper proposes to use the model-checking approach based on timed automata to compute the exact worstcase end-to-end delays and two case studies are presented
Exact worst-case communication delay analysis of AFDX network
The main objective of this thesis is to provide methodologies for finding exact worst case end to end communication delays of AFDX network. Presently, only pessimistic upper bounds of these delays can be calculated by using Network Calculus and Trajectory approach. To achieve this goal, different existing tools and approaches have been analyzed in the context of this thesis. Based on this analysis, it is deemed necessary to develop new approaches and algorithms. First, Model checking with existing well established real time model checking tools are explored, using timed automata. Then, exhaustive simulation technique is used with newly developed algorithms and their software implementation in order to find exact worst case communication delays of AFDX network. All this research work has been applied on real life implementation of AFDX network, allowing us to validate our research work on industrial scale configuration of AFDX network such as used on Airbus A380 aircraft
Ethernet-based AFDX simulation and time delay analysis
Nowadays, new civilian aircraft have applied new technology and the amount of embedded systems and functions raised. Traditional avionics data buses design canât meet the new transmission requirements regarding weight and complexity due to the number of needed buses. On the other hand, Avionics Full Duplex Switched Ethernet (AFDX) with sufficient bandwidth and guaranteed services is considered as the next generation of avionics data bus. One of the important issues in Avionics Full Duplex Switched Ethernet is to ensure the data total time delay to meet the requirements of the safety-critical systems on aircraft such as flight control system. This research aims at developing an AFDX time delay model which can be used to analyse the total time delay of the AFDX network. By applying network calculus approach, both (Ï,Ï) model and Generic Cell Rate Algorithm (GCRA) model are introduced. For tighter time-delay result, GCRA model is applied. Meanwhile, the current AFDX network simulation platform, FACADE, will be enhanced by adding new functions. Moreover, avionics application simulation modules are developed to exchange data with FACADE. The total time delay analysis will be performed on the improved FACADE to validate this AFDX network simulation platform in several scenarios. Moreover, each scenario is appropriated to study the association between total time delay performance and individual variable. The results from updated FACADE reflect the correlation between total time delay and certain variables. Larger BAG and more switches between source and destination end systems introduce larger total time delay while Lmax could also affect the total time delay. However, the results illustrate that the total time delays from updated FACADE are much larger than GCRA time delay model which could up to 10 times which indicates that this updated FACADE needs further improvement
Determinism Enhancement and Reliability Assessment in Safety Critical AFDX Networks
RĂSUMĂ AFDX est une technologie basĂ©e sur Ethernet, qui a Ă©tĂ© dĂ©veloppĂ©e pour rĂ©pondre aux dĂ©fis qui dĂ©coulent du nombre croissant dâapplications qui transmettent des donnĂ©es de criticitĂ© variable dans les systĂšmes modernes dâavionique modulaire intĂ©grĂ©e (Integrated Modular
Avionics). Cette technologie de sĂ©curitĂ© critique a Ă©tĂ© notamment normalisĂ©e dans la partie 7 de la norme ARINC 664, dont le but est de dĂ©finir un rĂ©seau dĂ©terministe fournissant des garanties de performance prĂ©visibles. En particulier, AFDX est composĂ© de deux rĂ©seaux redondants, qui fournissent la haute fiabilitĂ© requise pour assurer son dĂ©terminisme. Le dĂ©terminisme de AFDX est principalement rĂ©alisĂ© par le concept de liens virtuels (Virtual Links), qui dĂ©finit une connexion unidirectionnelle logique entre les points terminaux (End Systems). Pour les liens virtuels, les limites supĂ©rieures des dĂ©lais de bout en bout peuvent ĂȘtre obtenues en utilisant des approches comme calcul rĂ©seau, mieux connu sous lâappellation Network Calculus. Cependant, il a Ă©tĂ© prouvĂ© que ces limites supĂ©rieures sont pessimistes dans de nombreux cas, ce qui peut conduire Ă une utilisation inefficace des ressources et augmenter la complexitĂ© de la conception du rĂ©seau. En outre, en raison de lâasynchronisme de leur fonctionnement, il existe plusieurs sources de non-dĂ©terminisme dans les rĂ©seaux AFDX. Ceci introduit un problĂšme en lien avec la dĂ©tection des dĂ©fauts en temps rĂ©el. En outre, mĂȘme si un mĂ©canisme de gestion de la redondance est utilisĂ© pour amĂ©liorer la fiabilitĂ© des rĂ©seaux AFDX, il y a un risque potentiel soulignĂ© dans la partie 7 de la norme ARINC 664. La situation citĂ©e peut causer une panne en dĂ©pit des transmissions redondantes dans certains cas particuliers. Par consĂ©quent, lâobjectif de cette thĂšse est dâamĂ©liorer la performance et la fiabilitĂ© des rĂ©seaux AFDX.
Tout dâabord, un mĂ©canisme fondĂ© sur lâinsertion de trames est proposĂ© pour renforcer le dĂ©terminisme de lâarrivĂ©e des trames au sein des rĂ©seaux AFDX. Parce que la charge du
rĂ©seau et la bande passante moyenne utilisĂ©e augmente due Ă lâinsertion de trames, une stratĂ©gie dâagrĂ©gation des Sub-Virtual Links est introduite et formulĂ©e comme un problĂšme
dâoptimisation multi-objectif. En outre, trois algorithmes ont Ă©tĂ© dĂ©veloppĂ©s pour rĂ©soudre le problĂšme dâoptimisation multi-objectif correspondant. Ensuite, une approche est introduite pour incorporer lâanalyse de la performance dans lâĂ©valuation de la fiabilitĂ© en considĂ©rant les violations des dĂ©lais comme des pannes.----------ABSTRACT AFDX is an Ethernet-based technology that has been developed to meet the challenges due to the growing number of data-intensive applications in modern Integrated Modular Avionics systems. This safety critical technology has been standardized in ARINC 664 Part 7, whose purpose is to define a deterministic network by providing predictable performance guarantees. In particular, AFDX is composed of two redundant networks, which provide the determinism
required to obtain the desired high reliability.
The determinism of AFDX is mainly achieved by the concept of Virtual Link, which defines a logical unidirectional connection from one source End System to one or more destination End Systems. For Virtual Links, the end-to-end delay upper bounds can be obtained by using the Network Calculus. However, it has been proved that such upper bounds are pessimistic in many cases, which may lead to an inefficient use of resources and aggravate network design
complexity. Besides, due to asynchronism, there exists a source of non-determinism in AFDX networks, namely frame arrival uncertainty in a destination End System. This issue introduces a problem in terms of real-time fault detection. Furthermore, although a redundancy management mechanism is employed to enhance the reliability of AFDX networks, there
still exist potential risks as pointed out in ARINC 664 Part 7, which may fail redundant transmissions in some special cases. Therefore, the purpose of this thesis is to improve the performance and the reliability of AFDX networks. First, a mechanism based on frame insertion is proposed to enhance the determinism of frame arrival within AFDX networks. As the network load and the average bandwidth used by a Virtual Link increase due to frame insertion, a Sub-Virtual Link aggregation strategy, formulated as a multi-objective optimization problem, is introduced. In addition, three algorithms have been developed to solve the corresponding multi-objective optimization problem. Next, an approach is introduced to incorporate performance analysis into reliability assessment
by considering delay violations as failures. This allowed deriving tighter probabilistic upper bounds for Virtual Links that could be applied in AFDX network certification. In order to conduct the necessary reliability analysis, the well-known Fault-Tree Analysis technique is employed and Stochastic Network Calculus is applied to compute the upper bounds with various probability limits
Worst-case delay analysis of real-time switched Ethernet networks with flow local synchronization
Les rĂ©seaux Ethernet commutĂ© full-duplex constituent des solutions intĂ©ressantes pour des applications industrielles. Mais le non-dĂ©terminisme dâun commutateur IEEE 802.1d, fait que lâanalyse pire cas de dĂ©lai de flux critiques est encore un problĂšme ouvert. Plusieurs mĂ©thodes ont Ă©tĂ© proposĂ©es pour obtenir des bornes supĂ©rieures des dĂ©lais de communication sur des rĂ©seaux Ethernet commutĂ© full duplex temps rĂ©els, faisant lâhypothĂšse que le trafic en entrĂ©e du rĂ©seau peut ĂȘtre bornĂ©. Le problĂšme principal reste le pessimisme introduit par la mĂ©thode de calcul de cette borne supĂ©rieure du dĂ©lai. Ces mĂ©thodes considĂšrent que tous les flux transmis sur le rĂ©seau sont indĂ©pendants. Ce qui est vrai pour les flux Ă©mis par des nĆuds sources diffĂ©rents car il nâexiste pas, dans le cas gĂ©nĂ©ral, dâhorloge globale permettant de synchroniser les flux. Mais pour les flux Ă©mis par un mĂȘme nĆud source, il est possible de faire lâhypothĂšse dâune synchronisation locale de ces flux. Une telle hypothĂšse permet de bĂątir un modĂšle plus prĂ©cis des flux et en consĂ©quence Ă©limine des scĂ©narios impossibles qui augmentent le pessimisme du calcul. Le sujet principal de cette thĂšse est dâĂ©tudier comment des flux pĂ©riodiques synchronisĂ©s par des offsets peuvent ĂȘtre gĂ©rĂ©s dans le calcul des bornes supĂ©rieures des dĂ©lais sur un rĂ©seau Ethernet commutĂ© temps-rĂ©el. Dans un premier temps, il sâagit de prĂ©senter lâimpact des contraintes dâoffsets sur le calcul des bornes supĂ©rieures des dĂ©lais de bout en bout. Il sâagit ensuite de prĂ©senter comment intĂ©grer ces contraintes dâoffsets dans les approches de calcul basĂ©es sur le Network Calculus et la mĂ©thode des Trajectoires. Une mĂ©thode Calcul RĂ©seau modifiĂ©e et une mĂ©thode Trajectoires modifiĂ©e sont alors dĂ©veloppĂ©es et les performances obtenues sont comparĂ©es. Le rĂ©seau avionique AFDX (Avionics Full-Duplex Switched Ethernet) est pris comme exemple dâun rĂ©seau Ethernet commutĂ© full-duplex. Une configuration AFDX industrielle avec un millier de flux est prĂ©sentĂ©e. Cette configuration industrielle est alors Ă©valuĂ©e Ă lâaide des deux approches, selon un choix dâallocation dâoffsets donnĂ©. De plus, diffĂ©rents algorithmes dâallocation des offsets sont testĂ©s sur cette configuration industrielle, pour trouver un algorithme dâallocation quasi-optimal. Une analyse de pessimisme des bornes supĂ©rieures calculĂ©es est alors proposĂ©e. Cette analyse est basĂ©e sur lâapproche des trajectoires (rendue optimiste) qui permet de calculer une sous-approximation du dĂ©lai pire-cas. La diffĂ©rence entre la borne supĂ©rieure du dĂ©lai (calculĂ©e par une mĂ©thode donnĂ©e) et la sous-approximation du dĂ©lai pire cas donne une borne supĂ©rieure du pessimisme de la mĂ©thode. Cette analyse fournit des rĂ©sultats intĂ©ressants sur le pessimisme des approches Calcul RĂ©seau et mĂ©thode des Trajectoires. La derniĂšre partie de la thĂšse porte sur une architecture de rĂ©seau temps rĂ©el hĂ©tĂ©rogĂšne obtenue par connexion de rĂ©seaux CAN via des ponts sur un rĂ©seau fĂ©dĂ©rateur de type Ethernet commutĂ©. Deux approches, une basĂ©e sur les composants et lâautre sur les Trajectoires sont proposĂ©es pour permettre une analyse des dĂ©lais pire-cas sur un tel rĂ©seau. La capacitĂ© de calcul dâune borne supĂ©rieure des dĂ©lais pire-cas dans le contexte dâune architecture hĂ©tĂ©rogĂšne est intĂ©ressante pour les domaines industriels. ABSTRACT : Full-duplex switched Ethernet is a promising candidate for interconnecting real-time industrial applications. But due to IEEE 802.1d indeterminism, the worst-case delay analysis of critical flows supported by such a network is still an open problem. Several methods have been proposed for upper-bounding communication delays on a real-time switched Ethernet network, assuming that the incoming traffic can be upper bounded. The main problem remaining is to assess the tightness, i.e. the pessimism, of the method calculating this upper bound on the communication delay. These methods consider that all flows transmitted over the network are independent. This is true for flows emitted by different source nodes since, in general, there is no global clock synchronizing them. But the flows emitted by the same source node are local synchronized. Such an assumption helps to build a more precise flow model that eliminates some impossible communication scenarios which lead to a pessimistic delay upper bounds. The core of this thesis is to study how local periodic flows synchronized with offsets can be handled when computing delay upper-bounds on a real-time switched Ethernet. In a first step, the impact of these offsets on the delay upper-bound computation is illustrated. Then, the integration of offsets in the Network Calculus and the Trajectory approaches is introduced. Therefore, a modified Network Calculus approach and a modified Trajectory approach are developed whose performances are compared on an Avionics Full-DupleX switched Ethernet (AFDX) industrial configuration with one thousand of flows. It has been shown that, in the context of this AFDX configuration, the Trajectory approach leads to slightly tighter end-to-end delay upper bounds than the ones of the Network Calculus approach. But offsets of local flows have to be chosen. Different offset assignment algorithms are then investigated on the AFDX industrial configuration. A near-optimal assignment can be exhibited. Next, a pessimism analysis of the computed upper-bounds is proposed. This analysis is based on the Trajectory approach (made optimistic) which computes an under-estimation of the worst-case delay. The difference between the upper-bound (computed by a given method) and the under-estimation of the worst-case delay gives an upper-bound of the pessimism of the method. This analysis gives interesting comparison results on the Network Calculus and the Trajectory approaches pessimism. The last part of the thesis, deals with a real-time heterogeneous network architecture where CAN buses are interconnected through a switched Ethernet backbone using dedicated bridges. Two approaches, the component-based approach and the Trajectory approach, are developed to conduct a worst-case delay analysis for such a network. Clearly, the ability to compute end-to-end delays upper-bounds in the context of heterogeneous network architecture is promising for industrial domains
Real-time performance analysis of a QoS based industrial embedded network
AFDX serves as a backbone network for transmission of critical avionic flows. This network is certified thanks to the WCTT analysis using Network Calculus (NC) approach. However, the pessimism introduced by NC approach often leads to an over-sized and eventually an underutilized network. The manufacturers envision to better use the available network resources by increasing occupancy rate of the AFDX network by allowing additional traffic from other critical and non-critical functions. Such harmonization of AFDX network with mixed criticality flows necessitates the use of QoS mechanism to satisfy the delay constraints in different classes of flow. In this thesis we study such QoS-aware network, in particular, based on DRR and WRR scheduling. We propose an optimal bandwidth distribution method that ensures the service required by critical flows while providing maximum service to other non-critical flows. We also propose an optimized NC approach to compute tight delay bounds. Our approach has led to computation of up to 40% tighter bounds, in an industrial AFDX configuration, as compared to the classical approach
Proceedings of Junior Researcher Workshop on Real-Time Computing
It is our great pleasure to welcome you to Junior Researcher Workshop on Real-Time Computing 2007, which is held conjointly with the 15th conference on Real-Time and Network Systems (RTNS'07). The first successful edition was held conjointly with the French Summer School on Real-Time Systems 2005 (http://etr05.loria.fr). Its main purpose is to bring together junior researchers (Ph.D. students, postdoc, ...) working on real-time systems. This workshop is a good opportunity to present our works and share ideas with other junior researchers and not only, since we will present our work to the audience of the main conference. In response to the call for papers, 14 papers were submitted and the international Program Committee provided detailed comments to improve these work-in-progress papers. We hope that our remarks will help the authors to submit improved long versions of theirs papers to the next edition of RTNS. JRWRTC'07 would not be possible without the generous contribution of many volunteers and institutions which supported RTNS'07. First, we would like to express our sincere gratitude to our sponsors for their financial support : Conseil GĂ©nĂ©ral de Meuthe et Moselle, Conseil RĂ©gional de Lorraine, CommunautĂ© Urbaine du Grand Nancy, UniversitĂ© Henri PoincarĂ©, Institut National Polytechnique de Lorraine and LORIA and INRIA Lorraine. We are thankful to Pascal Mary for authorizing us to use his nice picture of âplace Stanislasâ for the proceedings and web site (many others are available at www.laplusbelleplacedumonde.com). Finally, we are most grateful to the local organizing committee that helped to organize the conference