Fully integrated millimeter-wave CMOS phased arrays

A decade ago, RF CMOS, even at low gigahertz frequencies, was considered an oxymoron by all but the most ambitious and optimistic. Today, it is a dominating force in most commercial wireless applications (e.g., cellular, WLAN, GPS, BlueTooth, etc.) and has proliferated into areas such as watt level power amplifiers (PA) [1] that have been the undisputed realm of compound semiconductors. This seemingly ubiquitous embracement of silicon and particularly CMOS is no accident. It stems from the reliable nature of silicon process technologies that make it possible to integrated hundreds of millions of transistors on a single chip without a single device failure, as evident in today’s microprocessors. Applied to microwave and millimeter wave applications, silicon opens the door for a plethora of new topologies, architectures, and applications. This rapid adoption of silicon is further facilitated by one’s ability to integrate a great deal of in situ digital signal processing and calibration [2]. Integration of high-frequency phased-array systems in silicon (e.g., CMOS) promises a future of low-cost radar and gigabit-per-second wireless communication networks. In communication applications, phased array provides an improved signal-to-noise ratio via formation of a beam and reduced interference generation for other users. The practically unlimited number of active and passive devices available on a silicon chip and their extremely tight control and excellent repeatability enable new architectures (e.g., [3]) that are not practical in compound semiconductor module-based approaches. The feasibility of such approaches can be seen through the discussion of an integrated 24GHz 4-element phased-array transmitter in 0.18μm CMOS [2], capable of beam forming and rapid beam steering for radar applications. On-chip power amplifiers (PA), with integrated 50Ω output matching, make this a fully-integrated transmitter. This CMOS transmitter and the 8-element phased-array SiGe receiver in [5], demonstrate the feasibility of 24GHz phased-array systems in silicon-based processes

A fully integrated 24-GHz phased-array transmitter in CMOS

This paper presents the first fully integrated 24-GHz phased-array transmitter designed using 0.18-/spl mu/m CMOS transistors. The four-element array includes four on-chip CMOS power amplifiers, with outputs matched to 50 /spl Omega/, that are each capable of generating up to 14.5 dBm of output power at 24 GHz. The heterodyne transmitter has a two-step quadrature up-conversion architecture with local oscillator (LO) frequencies of 4.8 and 19.2 GHz, which are generated by an on-chip frequency synthesizer. Four-bit LO path phase shifting is implemented in each element at 19.2 GHz, and the transmitter achieves a peak-to-null ratio of 23 dB with raw beam-steering resolution of 7/spl deg/ for radiation normal to the array. The transmitter can support data rates of 500 Mb/s on each channel (with BPSK modulation) and occupies 6.8 mm /spl times/ 2.1 mm of die area

The Class-E/F Family of ZVS Switching Amplifiers

A new family of switching amplifiers, each member having some of the features of both class E and inverse F, is introduced. These class-E/F amplifiers have class-E features such as incorporation of the transistor parasitic capacitance into the circuit, exact truly switching time-domain solutions, and allowance for zero-voltage-switching operation. Additionally, some number of harmonics may be tuned in the fashion of inverse class F in order to achieve more desirable voltage and current waveforms for improved performance. Operational waveforms for several implementations are presented, and efficiency estimates are compared to class-E

Novel CCII-based Field Programmable Analog Array and its Application to a Sixth-Order Butterworth LPF

In this paper, a field programmable analog array (FPAA) is proposed. The proposed FPAA consists of seven configurable analog blocks (CABs) arranged in a hexagonal lattice such that the CABs are directly connected to each other. This structure improves the overall frequency response of the chip by decreasing the parasitic capacitances in the signal path. The CABS of the FPAA is based on a novel fully differential digitally programmable current conveyor (DPCCII). The programmability of the DPCCII is achieved using digitally controlled three-bit MOS ladder current division network. No extra biasing circuit is required to generate specific analog control voltage signals. The DPCCII has constant standby power consumption, offset voltage, bandwidth and harmonic distortions over all its programming range. A sixth-order Butterworth tunable LPF suitable for WLAN/WiMAX receivers is realized on the proposed FPAA. The filter power consumption is 5.4mW from 1V supply; it’s cutoff frequency is tuned from 5.2 MHz to 16.9 MHz. All the circuits are realized using 90nm CMOS technology from TSMC. All simulations are carried out using Cadence

Distributed active transformer - a new power-combining andimpedance-transformation technique

In this paper, we compare the performance of the newly introduced distributed active transformer (DAT) structure to that of conventional on-chip impedance-transformations methods. Their fundamental power-efficiency limitations in the design of high-power fully integrated amplifiers in standard silicon process technologies are analyzed. The DAT is demonstrated to be an efficient impedance-transformation and power-combining method, which combines several low-voltage push-pull amplifiers in series by magnetic coupling. To demonstrate the validity of the new concept, a 2.4-GHz 1.9-W 2-V fully integrated power-amplifier achieving a power-added efficiency of 41% with 50-Ω input and output matching has been fabricated using 0.35-μm CMOS transistor

Realization of a single-chip, SiGe:C-based power amplifier for multi-band WiMAX applications

A fully-integrated Multi-Band PA using 0.25 μm SiGe:C process with an output power of above 25 dBm is presented. The behaviour of the amplifier has been optimized for multi-band operation covering, 2.4 GHz, 3.6 GHz and 5.4 GHz (UWB-WiMAX) frequency bands for higher 1-dB compression point and efficiency. Multi-band operation is achieved using multi-stage topology. Parasitic components of active devices are also used as matching components, in turn decreasing the number of matching component. Measurement results of the PA provided the following performance parameters: 1-dB compression point of 20.5 dBm, gain value of 23 dB and efficiency value of %7 operation for the 2.4 GHz band; 1-dB compression point of 25.5 dBm, gain value of 31.5 dB and efficiency value of %17.5 for the 3.6 GHz band; 1-dB compression point of 22.4 dBm, gain value of 24.4 dB and efficiency value of %9.5 for the 5.4 GHz band. Measurement results show that using multi-stage topologies and implementing each parasitic as part of the matching network component has provided a wider-band operation with higher output power levels, above 25 dBm, with SiGe:C process

Theory Based on Device Current Clipping to Explain and Predict Performance Including Distortion of Power Amplifiers for Wireless Communication Systems

Power amplifiers are critical components in wireless communication systems that need to have high efficiency, in order to conserve battery life and minimise heat generation, and at the same time low distortion, in order to prevent increase of bit error rate due to constellation errors and adjacent channel interference. This thesis is aimed at meeting a need for greater understanding of distortion generated by power amplifiers of any technology, in order to help designers manage better the trade-off between obtaining high efficiency and low distortion. The theory proposed in this thesis to explain and predict the performance of power amplifiers, including distortion, is based on analysis of clipping of the power amplifier device current, and it is a major extension of previous clipping analyses, that introduces many key definitions and concepts. Distortion and other power amplifier metrics are determined in the form of 3-D surfaces that are plotted against PA class, which is determined by bias voltage, and input signal power level. It is shown that the surface of distortion exhibits very high levels due to clipping in the region where efficiency is high. This area of high distortion is intersected by a valley that is ‘L’-shaped. The 'L'-shaped valley is subject to a rotation that depends on the softness of the cut-off of the power amplifier device transfer characteristic. The distortion surface with rotated 'L'-shaped valley leads to predicted curves for distortion versus input signal power that match published measured curves for power amplifiers even using very simple device models. The distortion versus input signal power curves have types that are independent of technology. In class C, there is a single deep null. In the class AB range, that is divided into three sub-ranges, there may be two deep nulls (sub-range AB(B)), a ledge (sub-range AB(A)) or a shallow null with varying depth (sub-range AB(AB))

A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s

This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115--225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step

Design architectures of the CMOS power amplifier for 2.4 GHz ISM band applications: An overview

Power amplifiers (PAs) are among the most crucial functional blocks in the radio frequency (RF) frontend for reliable wireless communication. PAs amplify and boost the input signal to the required output power. The signal is amplified to make it sufficiently high for the transmitter to propagate the required distance to the receiver. Attempted advancements of PA have focused on attaining high-performance RF signals for transmitters. Such PAs are expected to require low power consumption while producing a relatively high output power with a high efficiency. However, current PA designs in nanometer and micrometer complementary metal–oxide semiconductor (CMOS) technology present inevitable drawbacks, such as oxide breakdown and hot electron effect. A well-defined architecture, including a linear and simple functional block synthesis, is critical in designing CMOS PA for various applications. This article describes the different state-of-the art design architectures of CMOS PA, including their circuit operations, and analyzes the performance of PAs for 2.4 GHz ISM (industrial, scientific, and medical) band applications

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio