Current-Mode Techniques for the Implementation of Continuous- and Discrete-Time Cellular Neural Networks

This paper presents a unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular neural networks (CNN) using CMOS current-mode analog techniques. The net input signals are currents instead of voltages as presented in previous approaches, thus avoiding the need for current-to-voltage dedicated interfaces in image processing tasks with photosensor devices. Outputs may be either currents or voltages. Cell design relies on exploitation of current mirror properties for the efficient implementation of both linear and nonlinear analog operators. These cells are simpler and easier to design than those found in previously reported CT and DT-CNN devices. Basic design issues are covered, together with discussions on the influence of nonidealities and advanced circuit design issues as well as design for manufacturability considerations associated with statistical analysis. Three prototypes have been designed for l.6-pm n-well CMOS technologies. One is discrete-time and can be reconfigured via local logic for noise removal, feature extraction (borders and edges), shadow detection, hole filling, and connected component detection (CCD) on a rectangular grid with unity neighborhood radius. The other two prototypes are continuous-time and fixed template: one for CCD and other for noise removal. Experimental results are given illustrating performance of these prototypes

DESIGN OF AN ENERGY-EFFICIENT CONSTANT DELAY LOGIC FOR LOW POWER APPLICATIONS

An Energy Efficient Constant Delay Logic (EE-CDL) is proposed in this thesis to reduce the power consumption for low power applications. The EE-CDL is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. It has a unique characteristic where the output is pre-evaluated before the inputs from the preceding stage are ready. The proposed logic style requires low power when compared to the existing CDL. The proposed circuit is designed and using 90-nm, CMOS technology file with supply voltage 1.2V. An inverter is designed using energy efficient feedthrough logic and simulated in MicroWind. The simulation result shows that the proposed logic reduces the power consumption by 88%, 83% and 56% when compared with FTL, Low Power FTL (LP-FTL) and Constant Delay Logic (CDL) respectively. The problem of requirement of inverter as in dynamic logic is completely eliminated in the proposed logic

Expansion of CMOS array design techniques

The important features of the multiport (double entry) automatic placement and routing programs for standard cells are described. Measured performance and predicted performance were compared for seven CMOS/SOS array types and hybrids designed with the high speed CMOS/SOS cell family. The CMOS/SOS standard cell data sheets are listed and described

Development of a digital electronic rebalance loop for a dry tuned-rotor two degree-of-freedom gyroscope

Digital electronic rebalance loops were designed and implemented in brassboard form to capture both X and Y axes of the Kearfott Gyroflex. The loops were width-modulated binary types using a 614.4 kHz keying signal and a 2.4 kHz sample frequency. The loops were designed for a torquing rate of 2 deg/sec (70.6 mA torquing current) and a data resolution of 23.4 milli-arc-sec per data pulse. Design considerations, implementation details, and preliminary experimental results are presented

Analysis and application of improved feedthrough logic

Continuous technology scaling and increased frequency of operation of VLSI circuits leads to increase in power density which raises thermal management problem. Therefore design of low power VLSI circuit technique is a challenging task without sacrificing its performance. This thesis presents the design of a low power dynamic circuit using a new CMOS domino logic family called feedthrough (FTL) logic. Dynamic logic circuits are more significant because of its faster speed and lesser transistor requirement as compared to static CMOS logic circuits. The need for faster circuits compels designers to use FTL as compared static and domino CMOS logic and the requirement of output inverter for cascading of various logic blocks in domino logic are eliminated in the proposed design. The proposed circuit for low power (LP-FTL) improves dynamic power consumption as compared to the existing FTL and to further improve its speed we propose another circuit (HS-FTL). This logic family improves speed at the cost of dynamic power consumption and area. Proposed modified FTL circuit families provide better PDP as compared to the existing FTL. Simulation results of both the proposed circuit using 0.18 µm, 1.8 V CMOS process technology indicate that the LP-FTL structure reduces the dynamic power approximately by 42% and the HS-FTL structure achieves a speed up- 1.4 for 10-stage of inverters and 8-bit ripple carry adder in comparison to existing FTL logic. Furthermore, we present various circuit design techniques to improve noise tolerance of the proposed FTL logic families. Noise in deep submicron technology limits the reliability and performance of ICs. The ANTE (average noise threshold energy) metric is used for the analysis of noise tolerance of proposed FTL. A 2-input NAND and NOR gate is designed by the proposed technique. Simulation results for a 2-input NAND gate at 0.18-µm, 1.8 V CMOS process technology show that the proposed noise tolerant circuit achieves 1.79X ANTE improvement along with the reduction in leakage power. Continuous scaling of technology towards the nanometer range significantly increases leakage current level and the effect of noise. This research can be further extended for performance optimization in terms of power, speed, area and noise immunity

A Monolithic Time Stretcher for Precision Time Recording

Identifying light mesons which contain only up/down quarks (pions) from those containing a strange quark (kaons) over the typical meter length scales of a particle physics detector requires instrumentation capable of measuring flight times with a resolution on the order of 20ps. In the last few years a large number of inexpensive, multi-channel Time-to-Digital Converter (TDC) chips have become available. These devices typically have timing resolution performance in the hundreds of ps regime. A technique is presented that is a monolithic version of ``time stretcher'' solution adopted for the Belle Time-Of-Flight system to address this gap between resolution need and intrinsic multi-hit TDC performance.Comment: 9 pages, 15 figures, minor corrections made, to appear as JINST_008

X-ray equipment for Lunar Receiving Laboratory, volume 1 Final report, Sep. 1968 - Apr. 1969

Design, fabrication, installation, and operation of X ray diffractometer and X ray spectrograph system for preliminary examination of lunar soil sample within Lunar Receiving Laborator

Design of a Torque Current Generator for Strapdown Gyroscopes

The design, analysis, and experimental evaluation of an optimum performance torque current generator for use with strapdown gyroscopes, is presented. Among the criteria used to evaluate the design were the following: (1) steady-state accuracy; (2) margins of stability against self-oscillation; (3) temperature variations; (4) aging; (5) static errors drift errors, and transient errors, (6) classical frequency and time domain characteristics; and (7) the equivalent noise at the input of the comparater operational amplifier. The DC feedback loop of the torque current generator was approximated as a second-order system. Stability calculations for gain margins are discussed. Circuit diagrams are shown and block diagrams showing the implementation of the torque current generator are discussed