448 research outputs found
A design approach for integrated CMOS LC-tank oscillators using bifurcation analysis
Electrical oscillators play a decisive role in integrated transceivers for wired and wireless communication systems. In this context the study of fully integrated differential VCOs has received attention. In this paper formulas for investigations of the stability as well as the amplitude of CMOS LC tank oscillators are derived, where an overall model of nonlinear gain elements is used. By means of these results we are able to present an improved design approach which gives a deeper insight into the functionality of LC tank VCOs
Design of a tunable multi-band differential LC VCO using 0.35 mu m SiGe BiCMOS technology for multi-standard wireless communication systems
In this paper, an integrated 2.2-5.7GHz multi-band differential LC VCO for multi-standard wireless communication systems was designed utilizing 0.35 mu m SiGe BiCMOS technology. The topology, which combines the switching inductors and capacitors together in the same circuit, is a novel approach for wideband VCOs. Based on the post-layout simulation results, the VCO can be tuned using a DC voltage of 0 to 3.3 V for 5 different frequency bands (2.27-2.51 GHz, 2.48-2.78 GHz, 3.22-3.53 GHz, 3.48-3.91 GHz and 4.528-5.7 GHz) with a maximum bandwidth of 1.36 GHz and a minimum bandwidth of 300 MHz. The designed and simulated VCO can generate a differential output power between 0.992 and -6.087 dBm with an average power consumption of 44.21 mW including the buffers. The average second and third harmonics level were obtained as -37.21 and -47.6 dBm, respectively. The phase noise between -110.45 and -122.5 dBc/Hz, that was simulated at 1 MHz offset, can be obtained through the frequency of interest. Additionally, the figure of merit (FOM), that includes all important parameters such as the phase noise, the power consumption and the ratio of the operating frequency to the offset frequency, is between -176.48 and -181.16 and comparable or better than the ones with the other current VCOs. The main advantage of this study in comparison with the other VCOs, is covering 5 frequency bands starting from 2.27 up to 5.76 GHz without FOM and area abandonment. Output power of the fundamental frequency changes between -6.087 and 0.992 dBm, depending on the bias conditions (operating bands). Based on the post-layout simulation results, the core VCO circuit draws a current between 2.4-6.3 mA and between 11.4 and 15.3 mA with the buffer circuit from 3.3 V supply. The circuit occupies an area of 1.477 mm(2) on Si substrate, including DC, digital and RF pads
A New Technique for the Design of Multi-Phase Voltage Controlled Oscillators
© 2017 World Scientific Publishing Company.In this work, a novel circuit structure for second-harmonic multi-phase voltage controlled oscillator (MVCO) is presented. The proposed MVCO is composed of (Formula presented.) ((Formula presented.) being an integer number and (Formula presented.)2) identical inductor–capacitor ((Formula presented.)) tank VCOs. In theory, this MVCO can provide 2(Formula presented.) different phase sinusoidal signals. A six-phase VCO based on the proposed structure is designed in a TSMC 0.18(Formula presented.)um CMOS process. Simulation results show that at the supply voltage of 0.8(Formula presented.)V, the total power consumption of the six-phase VCO circuit is about 1(Formula presented.)mW, the oscillation frequency is tunable from 2.3(Formula presented.)GHz to 2.5(Formula presented.)GHz when the control voltage varies from 0(Formula presented.)V to 0.8(Formula presented.)V, and the phase noise is lower than (Formula presented.)128(Formula presented.)dBc/Hz at 1(Formula presented.)MHz offset frequency. The proposed MVCO has lower phase noise, lower power consumption and more outputs than other related works in the literature.Peer reviewedFinal Accepted Versio
Design of a 4.2-5.4 GHz Differential LC VCO using 0.35 m SiGe BiCMOS Technology
In this paper, a 4.2-5.4 GHz, Gm LC voltage controlled oscillator (VCO) for IEEE 802.11a standard is presented. The circuit is designed with AMS 0.35´m SiGe BiCMOS process that includes high-speed SiGe Heterojunction Bipolar Transistors (HBTs). Phase noise is -110.7 dBc/Hz at 1MHz offset from 5.4 GHz carrier frequency and -113.5 dBc/Hz from 4.2 GHz carrier frequency. A linear, 1200 MHz tuning range is obtained utilizing accumulation-mode varactors. Phase noise is relatively low due to taking the advantage of differential tuning concept. Output power of the fundamental frequency changes between 4.8 dBm and 5.5 dBm depending on the tuning voltage. The circuit draws 2 mA without buffers and 14.5 mA from 2.5 V supply including buffer circuits leading to a total power dissipation of 36.25 mW. The circuit occupies an area of 0.6 mm2 on Si substrate including RF and DC pads
A new resonant circuit for 2.45 GHz LC VCO with linear frequency tuning
A new MOS varactor bank is proposed to implement a 2.45 GHz SiGe BiCMOS LC-tank voltage controlled oscillator (VCO) with linear frequency tuning. Compared to a conventional VCO, the proposed technique improves the quality factor of the LC-tank while preserving the linearity of the circuit. Realized in 0.25-μm SiGe
BiCMOS technology, VCO exhibits 35% VCO gain (KVCO) variation from 2.29 to 2.66 GHz with a 16% tuning ratio. The VCO also exhibits a phase noise of -113 dBc/Hz at 1 MHz offset frequency and consumes 1.7 mA from 1.8 V supply
Concepts and methods in optimization of integrated LC VCOs
Underlying physical mechanisms controlling the noise properties of oscillators are studied. This treatment shows the importance of inductance selection for oscillator noise optimization. A design strategy centered around an inductance selection scheme is executed using a practical graphical optimization method to optimize phase noise subject to design constraints such as power dissipation, tank amplitude, tuning range, startup condition, and diameters of spiral inductors. The optimization technique is demonstrated through a design example, leading to a 2.4-GHz fully integrated, LC voltage-controlled oscillator (VCO) implemented using 0.35-μm MOS transistors. The measured phase-noise values are -121, -117, and -115 dBc/Hz at 600-kHz offset from 1.91, 2.03, and 2.60-GHz carriers, respectively. The VCO dissipates 4 mA from a 2.5-V supply voltage. The inversion mode MOSCAP tuning is used to achieve 26% of tuning range. Two figures of merit for performance comparison of various oscillators are introduced and used to compare this work to previously reported results
A Noise-Shifting Differential Colpitts VCO
A novel noise-shifting differential Colpitts VCO is presented. It uses current switching to lower phase noise by cyclostationary noise alignment and improve the start-up condition. A design strategy is also devised to enhance the phase noise performance of quadrature coupled oscillators. Two integrated VCOs are presented as design examples
Design and Implementation of A 6-GHz Array of Four Differential VCOs Coupled Through a Resistive Network
International audienceThis paper presents the design and the implementation of a fully monolithic coupled-oscillator array, operating at 6 GHz with close to zero coupling phase, in 0.25 μm BICMOS SiGe process. This array is made of four LC-NMOS differential VCOs coupled through a resistor. The single LC-NMOS VCO structure is designed and optimized in terms of phase noise with a graphical optimization approach while satisfying design constraints. At 2.5 V power supply voltage, and a power dissipation of only 125 mW, the coupled oscillators array features a simulated phase noise of -127.3 dBc/Hz at 1 MHz frequency offset from a 6 GHz carrier, giving a simulated phase progression that was continuously variable over the range -64° < Δphi <64 ° and -116° < Δphi < 116°. This constant phase progression can be established by slightly detuning the peripheral array elements, while maintaining mutual synchronization
Analysis of the high frequency substrate noise effects on LC-VCOs
La integració de transceptors per comunicacions de radiofreqüència en CMOS pot quedar seriosament limitada per la interacció entre els seus blocs, arribant a desaconsellar la utilització de un únic dau de silici. El soroll d’alta freqüència generat per certs blocs, com l’amplificador de potencia, pot viatjar pel substrat i amenaçar el correcte funcionament de l’oscil·lador local. Trobem tres raons importants que mostren aquest risc d’interacció entre blocs i que justifiquen la necessitat d’un estudi profund per minimitzar-lo. Les característiques del substrat fan que el soroll d’alta freqüència es propagui m’és fàcilment que el de baixa freqüència. Per altra banda, les estructures de protecció perden eficiència a mesura que la freqüència augmenta. Finalment, el soroll d’alta freqüència que arriba a l’oscil·lador degrada al seu correcte comportament. El propòsit d’aquesta tesis és analitzar en profunditat la interacció entre el soroll d’alta freqüència que es propaga pel substrat i l’oscil·lador amb l’objectiu de poder predir, mitjançant un model, l’efecte que aquest soroll pot tenir sobre el correcte funcionament de l’oscil·lador. Es volen proporcionar diverses guies i normes a seguir que permeti als dissenyadors augmentar la robustesa dels oscil·ladors al soroll d’alta freqüència que viatja pel substrat.
La investigació de l’efecte del soroll de substrat en oscil·ladors s’ha iniciat des d’un punt de vista empíric, per una banda, analitzant la propagació de senyals a través del substrat i avaluant l’eficiència d’estructures per bloquejar aquesta propagació, i per altra, determinant l’efecte d’un to present en el substrat en un oscil·lador. Aquesta investigació ha mostrat que la injecció d’un to d’alta freqüència en el substrat es pot propagar fins arribar a l’oscil·lador i que, a causa del ’pulling’ de freqüència, pot modular en freqüència la sortida de l’oscil·lador. A partir dels resultats de l’anàlisi empíric s’ha aportat un model matemàtic que permet predir l’efecte del soroll en l’oscil·lador. Aquest model té el principal avantatge en el fet de que està basat en paràmetres físics de l’oscil·lador o del soroll, permetent determinar les mesures que un dissenyador pot prendre per augmentar la robustesa de l’oscil·lador així com les conseqüències que aquestes mesures tenen sobre el seu funcionament global (trade-offs). El model ha estat comparat tant amb simulacions com amb mesures reals demostrant ser molt precís a l’hora de predir l’efecte del soroll de substrat.
La utilitat del model com a eina de disseny s’ha demostrat en dos estudis. Primerament, les conclusions del model han estat aplicades en el procés de disseny d’un oscil·lador d’ultra baix consum a 2.5GHz, aconseguint un oscil·lador robust al soroll de substrat d’alta freqüència i amb característiques totalment compatibles amb els principals estàndards de comunicació en aquesta banda.
Finalment, el model s’ha utilitzat com a eina d’anàlisi per avaluar la causa de les diferències, en termes de robustesa a soroll de substrat, mesurades en dos oscil·ladors a 60GHz amb dues diferents estratègies d’apantallament de l’inductor del tanc de ressonant, flotant en un cas i connectat a terra en l’altre. El model ha mostrat que les diferències en robustesa són causades per la millora en el factor de qualitat i en l’amplitud d’oscil·lació i no per un augment en l’aïllament entre tanc i substrat.
Per altra banda, el model ha demostrat ser vàlid i molt precís inclús en aquest rang de freqüència tan extrem. el principal avantatge en el fet de que està basat en paràmetres físics de l’oscil·lador o del soroll, permetent determinar les mesures que un dissenyador pot prendre per augmentar la robustesa de l’oscil·lador així com les conseqüències que aquestes mesures tenen sobre el seu funcionament global
(trade-offs). El model ha estat comparat tant amb simulacions com amb mesures reals demostrant ser molt precís a l’hora de predir l’efecte del soroll de substrat.
La utilitat del model com a eina de disseny s’ha demostrat en dos estudis. Primerament, les conclusions del model han estat aplicades en el procés de disseny d’un oscil·lador d’ultra baix consum a 2.5GHz, aconseguint un oscil·lador robust al soroll de substrat d’alta freqüència i amb característiques totalment compatibles amb els principals estàndards de comunicació en aquesta banda.
Finalment, el model s’ha utilitzat com a eina d’anàlisi per avaluar la causa de les diferències, en termes de robustesa a soroll de substrat, mesurades en dos oscil·ladors a 60GHz amb dues diferents estratègies d’apantallament de l’inductor del tanc de ressonant, flotant en un cas i connectat a terra en l’altre. El model ha mostrat que les diferències en robustesa són causades per la millora en el factor de qualitat i en l’amplitud d’oscil·lació i no per un augment en l’aïllament entre tanc i substrat.
Per altra banda, el model ha demostrat ser vàlid i molt precís inclús en aquest rang de freqüència tan extrem.The integration of transceivers for RF communication in CMOS can be seriously limited by the interaction between their blocks, even advising against using a single silicon die. The high frequency noise generated by some of the blocks, like the power amplifier, can travel through the substrate, reaching the local oscillator and threatening its correct performance. Three important reasons can be stated that show the risk of the single die integration. Noise propagation is easier the higher the frequency. Moreover, the protection structures lose efficiency as the noise frequency increases. Finally, the high frequency noise that reaches the local oscillator degrades its performance. The purpose of this thesis is to deeply analyze the interaction between the high frequency substrate noise and the oscillator with the objective of being able to predict, thanks to a model, the effect that this noise may have over the correct behavior of the oscillator. We want to provide some guidelines to the designers to allow them to increase the robustness of the oscillator to high frequency substrate noise.
The investigation of the effect of the high frequency substrate noise on oscillators has started from an empirical point of view, on one hand, analyzing the noise propagation through the substrate and evaluating the efficiency of some structures to block this propagation, and on the other hand, determining the effect on an oscillator of a high frequency noise tone present in the substrate. This investigation has shown that the injection of a high frequency tone in the substrate can reach the oscillator and, due to a frequency pulling effect, it can modulate in frequency the output of the oscillator. Based on the results obtained during the empirical analysis, a mathematical model to predict the effect of the substrate noise on the oscillator has been provided. The main advantage of this model is the fact that it is based on physical parameters of the oscillator and of the noise, allowing to determine the measures that a designer can take to increase the robustness of the oscillator as well as the consequences (trade-offs) that these measures have over its global performance. This model has been compared against both, simulations and real measurements, showing a very high accuracy to predict the effect of the high frequency substrate noise.
The usefulness of the presented model as a design tool has been demonstrated in two case studies. Firstly, the conclusions obtained from the model have been applied in the design of an ultra low power consumption 2.5 GHz oscillator robust to the high frequency substrate noise with characteristics which make it compatible with the main communication standards in this frequency band. Finally, the model has been used as an analysis tool to evaluate the cause of the differences, in terms of performance degradation due to substrate noise, measured in two 60 GHz oscillators with two different tank inductor shielding strategies, floating and grounded. The model has determined that the robustness differences are caused by the improvement in the tank quality factor and in the oscillation amplitude and no by an increased isolation between the tank and the substrate. The model has shown to be valid and very accurate even in these extreme frequency range.Postprint (published version
Design of VCOs in Deep Sub-micron Technologies
This work will present a more accurate frequency prediction model for single-ended ring oscillators (ROs), a case-study comparing different ROs, and a design method for LC voltage-controlled oscillators (LCVCOs) that uses a MATLAB script based on analytical equations to output a graphical design space showing performance characteristics as a function of design parameters. Using this method, design trade-offs become clear, and the designer can choose which performance characteristics to optimize. These methods were used to design various topologies of ring oscillators and LCVCOs in the GlobalFoundries 28 nm HPP CMOS technology, comparing the performance between different topologies based on simulation results. The results from the MATLAB design script were compared to simulation results as well to show the effectiveness of the design methods.
Three varieties of 5 GHz voltage controlled ring oscillators were designed in the GlobalFoundries 28 nm HPP CMOS technology. The first is a low current low dropout regulator (LDO) tuned ring oscillator designed with thin oxide devices and a 0.85 V supply. The second is a high current LDO-tuned ring oscillator designed with medium oxide devices and a 1.5 V supply. The third is varactor-tuned ring oscillator with no LDO, and 0.85 V supply. Performance comparison of these ring oscillator systems are presented, outlining trade-offs between tuning range, phase noise, power dissipation, and area. The varactor-tuned ring oscillator exhibits 8.89 dBc/Hz (with power supply noise) and 16.27 dBc/Hz (without power supply noise) improvement in phase noise over the best-performing LDO-tuned ring oscillator. There are advantages in average power dissipation and area for a minimal tradeoff in tuning range with the varactor-tuned ring oscillator.
Four multi-GHz LCVCOs were designed in the GlobalFoundries 28 nm HPP CMOS technology: 15 GHz varactor-tuned NMOS-only, 9 GHz varactor-tuned self-biased CMOS, 14.2 GHz digitally-tuned NMOS-only, and 8.2 GHz digitally-tuned self-biased CMOS. As a design method, analytical ex-pressions describing tuning range, tank amplitude constraint, and startup condition were used in MATLAB to output a graphical view of the design space for both NMOS-only and CMOS LCVCOs, with maximum varactor capacitance on the y-axis and NMOS transistor width on the x-axis. Phase noise was predicted as well. In addition to the standard varactor control voltage tuning method, digitally-tuned implementations of both NMOS and CMOS LCVCOs are presented. The performance aspects of all designed LCVCOs are compared. Both varactor-tuned and digitally-tuned NMOS LCVCOs have lower phase noise, lower power consumption, and higher tuning range than both CMOS topologies. The varactor-tuned NMOS LCVCO has the lowest phase noise of -97 dBc/Hz at 1 MHz offset from 15 GHz center frequency, FOM of -172.20 dBc/Hz, and FOMT of -167.76 dBc/Hz. The digitally-tuned CMOS LCVCO has the greatest tuning range at 10%. Phase noise is improved by 3 dBc/Hz with the digitally-tuned CMOS topology over varactor-tuned CMOS
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