492 research outputs found
Hard Exudate Extraction from Fundus Images using Watershed Transform
Diabetic Retinopathy is a medical condition which affects the eyes due to increased blood sugar levels. This is characterized by presence of exudates - deposits of lipids in the posterior pole of the retina. If this ailment is not treated in earlier stages these deposits can cause blurred vision or even permanent blindness. This paper concentrates on extraction of hard exudates and optic disc from the retinal images of eyes using Marker based Watershed approach, which uses the minima imposition method to create mask and marker. The varying contrast across all the images has been taken care by a non-linear equation. Once these bright objects have been extracted from fundus images, area estimation is performed to eliminate the optic disk, thus retaining only exudates. These images have been procured from publicly available databases. Though software systems are easy to install, they prove to be expensive in terms of time and cost; thus this method has also been implemented on FPGA for an on-chip solution. The precision and sensitivity for exudate extraction sans optic disk are found to be 92.4% and 83.78% respectively. Though other techniques exist which provide better accuracy, the method described in this paper is found to be hardware friendly in comparison with other proven methods. Few steps of the algorithm developed are implemented on FPGA to provide an embedded system approach to this work, considering the advantages of a hardware-software combination
Fast and efficient FPGA implementation of connected operators
International audienceThe Connected Component Tree (CCT)-based operators play a central role in the development of new algorithms related to image processing applications such as pattern recognition, video-surveillance or motion extraction. The CCT construction, being a time consuming task (about 80% of the application time), these applications remain far-off mobile embedded systems. This paper presents its efficient FPGA implementation suited for embedded systems. Three main contributions are discussed: an efficient data structure proposal adapted to representing the CCT in embedded systems, a memory organization suitable for FPGA implementation by using on-chip memory and a customizable hardware accelerator architecture for CCT-based applications
Image Based Congestion Detection Algorithms And Its Real Time Implementation
In recent years, intelligent traffic management have included many new fields
and features. One of the important fields which directly affect our life is the traffic
congestion alert system i.e. a complete system which is able to detect congestion and
alert concerned parties to save time, fuel and man power. Recent methods in congestion
detection need prior knowledge about the road or several minutes are taken to produce
results or a huge infrastructure is needed to implement the system, even then, not in real
time. Most of the current studies in image processing are not reliable for real
implementation because they either lack accuracy or do not work in real time. The
proposed system aims to find a new congestion detection method that has high accuracy
and having real time processing time, also it aims to demonstrate the transmit/receive
process for image transmission using Software Defined Radio. The proposed system
offers a complete detection and alert network that captures an image of the road
situation, determine whether the road is congested or clear and finally report the results
wirelessly to the traffic management bodies to take action and inform people to avoid
the congested areas in real time. The proposed system uses a fast and reliable method to
detect traffic congestions. The methodology includes vehicle detection by using
backlight pairing feature algorithm and modified Watershed algorithm. The results
returned by the algorithms are transmitted and received wirelessly using the SFFSDR
platform, including the use of RF, FPGA, and DSP modules for variable distances. The
system shows an accuracy of detection up to 98-98.8% with time consumption of up to 3
seconds which make it feasible for real time implementation. The wireless system has
been tested using different distances between SDR antennas. The received power, bit
loss percentage and PSNR for the received image have been obtained, results shows a
35dB PSNR for normal distance between SDR antennas (20cm) and 7dB for 150cm,
while bits are totally lost when reaching 200cm
Real-Time Vision System for License Plate Detection and Recognition on FPGA
Rapid development of the Field Programmable Gate Array (FPGA) offers an alternative way to provide acceleration for computationally intensive tasks such as digital signal and image processing. Its ability to perform parallel processing shows the potential in implementing a high speed vision system. Out of numerous applications of computer vision, this paper focuses on the hardware implementation of one that is commercially known as Automatic Number Plate Recognition (ANPR).Morphological operations and Optical Character Recognition (OCR) algorithms have been implemented on a Xilinx Zynq-7000 All-Programmable SoC to realize the functions of an ANPR system. Test results have shown that the designed and implemented processing pipeline that consumed 63 % of the logic resources is capable of delivering the results with relatively low error rate. Most importantly, the computation time satisfies the real-time requirement for many ANPR applications
Implementation of watershed based image segmentation algorithm in FPGA
The watershed algorithm is a commonly used method of solving the image segmentation problem. However, of the many variants of the watershed algorithm not all are equally well suited for hardware implementation. Different algorithms are studied and the watershed algorithm based on connected components is selected for the implementation, as it exhibits least computational complexity, good segmentation quality and can be implemented in the FPGA. It has simplified memory access compared to all other watershed based image segmentation algorithms. This thesis proposes a new hardware implementation of the selected watershed algorithm. The main aim of the thesis is to implement image segmentation algorithm in a FPGA which requires minimum hardware resources, low execution time and is suitable for use in real time applications.
A pipelined architecture of algorithm is designed, implemented in VHDL and synthesized for Xilinx Virtex-4 FPGA. In the implementation, image is loaded to external memory and algorithm is repeatedly applied to the image. To overcome the problem of over-segmentation, pre-processing step is used before the segmentation and implemented in the pipelined architecture. The pipelined architecture of pre-processing stage can be operated at up to 228 MHz. The computation time for a 512 x 512 image is about 35 to 45 ms using one pipelined segmentation unit. A proposal of parallel architecture is discussed which uses multiple segmentation units and is fast enough for the real time applications. The implemented and proposed architectures are excellent candidates to use for different applications where high speed performance is needed
Summer 2008 Research Symposium Abstract Book
Summer 2008 volume of abstracts for science research projects conducted by Trinity College students
UNet Based Pipeline for Lung Segmentation from Chest X-Ray Images
Biomedical image segmentation is one of the fastest growing fields which has
seen extensive automation through the use of Artificial Intelligence. This has
enabled widespread adoption of accurate techniques to expedite the screening
and diagnostic processes which would otherwise take several days to finalize.
In this paper, we present an end-to-end pipeline to segment lungs from chest
X-ray images, training the neural network model on the Japanese Society of
Radiological Technology (JSRT) dataset, using UNet to enable faster processing
of initial screening for various lung disorders. The pipeline developed can be
readily used by medical centers with just the provision of X-Ray images as
input. The model will perform the preprocessing, and provide a segmented image
as the final output. It is expected that this will drastically reduce the
manual effort involved and lead to greater accessibility in
resource-constrained locations.Comment: 6 Page
A real-time computer vision library for heterogeneous processing environments
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 69-70).With a variety of processing technologies available today, using a combination of different technologies often provides the best performance for a particular task. However, unifying multiple processors with different instruction sets can be a very ad hoc and difficult process. The Open Component Portability Infrastructure (OpenCPI) provides a platform that simplifies programming heterogeneous processing applications requiring a mix of processing technologies. These include central processing units (CPU), graphics processing units (GPU), field-programmable gate arrays (FPGA), general-purpose processors (GPP), digital signal processors (DSP), and high-speed switch fabrics. This thesis presents the design and implementation of a computer vision library in the OpenCPI framework, largely based on Open Source Computer Vision (OpenCV), a widely used library of optimized software components for real-time computer vision. The OpenCPI-OpenCV library consists of a collection of resource-constrained C language (RCC) workers, along with applications demonstrating how these workers can be combined to achieve the same functionality as various OpenCV library functions. Compared with applications relying solely on OpenCV, analogous OpenCPI applications can be constructed from many workers, often resulting in greater parallelization if run on multi-core platforms. Future OpenCPI computer vision applications will be able to utilize these existing RCC workers, and a subset of these workers can potentially be replaced with alternative implementations, e.g. on GPUs or FPGAs.by Tony J. Liu.M.Eng
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