Extended-Range Second-Order Incremental Sigma-Delta ADC

A single-stage two-steps Extended-Range Second-Order Incremental ADC in 0.13um CMOS technology is presented here which achieves a Signal-to-Noise and Distortion Ratio (SNDR) as large as 73 dB. The proposed architecture of Extended-Range ADC based on Second-order multi-bit CIFF Incremental ADC reuses the IADC structure for coarse (input signal) as well as fine (residue) quantization without need of employment of explicit second ADC thereby minimizing power consumption and area occupancy. With a clock frequency of 80 MHz, the complete ERADC achieves in extracted simulation a peak SNDR of 73 dB at a data rate of 3.2 MS/s (25 clock cycles per conversion).A single-stage two-steps Extended-Range Second-Order Incremental ADC in 0.13um CMOS technology is presented here which achieves a Signal-to-Noise and Distortion Ratio (SNDR) as large as 73 dB. The proposed architecture of Extended-Range ADC based on Second-order multi-bit CIFF Incremental ADC reuses the IADC structure for coarse (input signal) as well as fine (residue) quantization without need of employment of explicit second ADC thereby minimizing power consumption and area occupancy. With a clock frequency of 80 MHz, the complete ERADC achieves in extracted simulation a peak SNDR of 73 dB at a data rate of 3.2 MS/s (25 clock cycles per conversion)

Ultra-low noise, high-frame rate readout design for a 3D-stacked CMOS image sensor

Due to the switch from CCD to CMOS technology, CMOS based image sensors have become smaller, cheaper, faster, and have recently outclassed CCDs in terms of image quality. Apart from the extensive set of applications requiring image sensors, the next technological breakthrough in imaging would be to consolidate and completely shift the conventional CMOS image sensor technology to the 3D-stacked technology. Stacking is recent and an innovative technology in the imaging field, allowing multiple silicon tiers with different functions to be stacked on top of each other. The technology allows for an extreme parallelism of the pixel readout circuitry. Furthermore, the readout is placed underneath the pixel array on a 3D-stacked image sensor, and the parallelism of the readout can remain constant at any spatial resolution of the sensors, allowing extreme low noise and a high-frame rate (design) at virtually any sensor array resolution. The objective of this work is the design of ultra-low noise readout circuits meant for 3D-stacked image sensors, structured with parallel readout circuitries. The readout circuit’s key requirements are low noise, speed, low-area (for higher parallelism), and low power. A CMOS imaging review is presented through a short historical background, followed by the description of the motivation, the research goals, and the work contributions. The fundamentals of CMOS image sensors are addressed, as a part of highlighting the typical image sensor features, the essential building blocks, types of operation, as well as their physical characteristics and their evaluation metrics. Following up on this, the document pays attention to the readout circuit’s noise theory and the column converters theory, to identify possible pitfalls to obtain sub-electron noise imagers. Lastly, the fabricated test CIS device performances are reported along with conjectures and conclusions, ending this thesis with the 3D-stacked subject issues and the future work. A part of the developed research work is located in the Appendices.Devido à mudança da tecnologia CCD para CMOS, os sensores de imagem em CMOS tornam se mais pequenos, mais baratos, mais rápidos, e mais recentemente, ultrapassaram os sensores CCD no que respeita à qualidade de imagem. Para além do vasto conjunto de aplicações que requerem sensores de imagem, o próximo salto tecnológico no ramo dos sensores de imagem é o de mudar completamente da tecnologia de sensores de imagem CMOS convencional para a tecnologia “3D-stacked”. O empilhamento de chips é relativamente recente e é uma tecnologia inovadora no campo dos sensores de imagem, permitindo vários planos de silício com diferentes funções poderem ser empilhados uns sobre os outros. Esta tecnologia permite portanto, um paralelismo extremo na leitura dos sinais vindos da matriz de píxeis. Além disso, num sensor de imagem de planos de silício empilhados, os circuitos de leitura estão posicionados debaixo da matriz de píxeis, sendo que dessa forma, o paralelismo pode manter-se constante para qualquer resolução espacial, permitindo assim atingir um extremo baixo ruído e um alto debito de imagens, virtualmente para qualquer resolução desejada. O objetivo deste trabalho é o de desenhar circuitos de leitura de coluna de muito baixo ruído, planeados para serem empregues em sensores de imagem “3D-stacked” com estruturas altamente paralelizadas. Os requisitos chave para os circuitos de leitura são de baixo ruído, rapidez e pouca área utilizada, de forma a obter-se o melhor rácio. Uma breve revisão histórica dos sensores de imagem CMOS é apresentada, seguida da motivação, dos objetivos e das contribuições feitas. Os fundamentos dos sensores de imagem CMOS são também abordados para expor as suas características, os blocos essenciais, os tipos de operação, assim como as suas características físicas e suas métricas de avaliação. No seguimento disto, especial atenção é dada à teoria subjacente ao ruído inerente dos circuitos de leitura e dos conversores de coluna, servindo para identificar os possíveis aspetos que dificultem atingir a tão desejada performance de muito baixo ruído. Por fim, os resultados experimentais do sensor desenvolvido são apresentados junto com possíveis conjeturas e respetivas conclusões, terminando o documento com o assunto de empilhamento vertical de camadas de silício, junto com o possível trabalho futuro

Design techniques for wideband low-power Delta-Sigma analog-to-digital converters

Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are traditionally used in high quality audio systems, instrumentation and measurement (I&M) and biomedical devices. With the continued downscaling of CMOS technology, they are becoming popular in wideband applications such as wireless and wired communication systems,high-definition television and radar systems. There are two general realizations of a ΔΣ modulator. One is based on the discrete-time (DT) switched-capacitor (SC) circuitry and the other employs continuous-time (CT) circuitry. Compared to a CT structure, the DT ΔΣ ADC is easier to analyze and design, is more robust to process variations and jitter noise, and is more flexible in the multi-mode applications. On the other hand, the CT ΔΣ ADC does not suffer from the strict settling accuracy requirement for the loop filter and thus can achieve lower power dissipation and higher sampling frequency than its DT counterpart. In this thesis, both DT and CT ΔΣ ADCs are investigated. Several design innovations, in both system-level and circuit-level, are proposed to achieve lower power consumption and wider signal bandwidth. For DT ΔΣ ADCs, a new dynamic-biasing scheme is proposed to reduce opamp bias current and the associated signal-dependent harmonic distortion is minimized by using the low-distortion architecture. The technique was verified in a 2.5MHz BW and 13bit dynamic range DT ΔΣ ADC. In addition, a second-order noise coupling technique is presented to save two integrators for the loop filter, and to achieve low power dissipation. Also, a direct-charge-transfer (DCT) technique is suggested to reduce the speed requirements of the adder, which is also preferable in wideband low-power applications. For CT ΔΣ ADCs, a wideband low power CT 2-2 MASH has been designed. High linearity performance was achieved by using a modified low-distortion technique, and the modulator achieves higher noise-shaping ability than the single stage structure due to the inter-stage gain. Also, the quantization noise leakage due to analog circuit non-idealities can be adaptively compensated by a designed digital calibration filter. Using a 90nm process, simulation of the modulator predicts a 12bit resolution within 20MHz BW and consumes only 25mW for analog circuitry. In addition, the noise-coupling technique is investigated and proposed for the design of CT ΔΣ ADCs and it is promising to achieve low power dissipation for wideband applications. Finally, the application of noise-coupling technique is extended and introduced to high-accuracy incremental data converters. Low power dissipation can be expected

Implementation and Analysis of Direct Torque Control for Permanent Magnet Synchronous Motor Using Gallium Nitride based Inverter

Permanent magnet synchronous machines (PMSMs) attract considerable attention in various industrial applications, such as electric and hybrid electric vehicles, due to their high efficiency and high-power density. In this thesis, the mathematical model of PMSM and two popular control strategies, field-oriented control (FOC) and direct torque control (DTC), are analyzed and compared. The results demonstrated that the DTC has better dynamic response in comparison to FOC. Moreover, DTC can eliminate the use of position sensor, which will save the cost of the PMSM drive system. Therefore, this thesis focuses on the design and implementation of high-performance DTC for PMSMs with a Gallium Nitride (GaN) based high switching frequency motor drive. First, the characteristics and operation principles of a PMSM are introduced. Then, the mathematical models of a PMSM under different coordinate systems are investigated. Consequently, a PMSM model is developed based on the dq rotating reference frame and implemented in the MATLAB/Simulink for validation. Two advanced PMSM control strategies, FOC and DTC, are investigated and compared in terms of control performance through comprehensive simulation studies and the results demonstrate that DTC has better dynamic performance. Conventional DTC contributes to higher torque ripple in the PMSM due to the limited switching frequency in a conventional semiconductor-based motor drive, which inevitably deteriorates the drive performance. Therefore, this thesis aims to reduce the torque ripple in the DTC based PMSM drive by using the new generation wide bandgap switching devices. More specifically, DTC is improved by using the optimized space vector pulse width modulation strategy and a higher switching frequency contributed by the GaN based motor drive. Finally, the proposed DTC-SVM based PMSM control strategy is implemented on the digital signal processor (DSP) and evaluated on the laboratory GaN based PMSM drive. Both the simulation and experimental results show that the proposed improvement in the DTC can further improve the PMSM drive performance