Regularity of Digits and Significant Digits of Random Variables

A random variable X is digit-regular (respectively, significant-digit-regular) if the probability that every block of k given consecutive digits (significant digits) appears in the b-adic expansion of X approaches b &supk; as the block moves to the right, for all integers b > 1 and k ? 1. Necessary and sufficient conditions are established, in terms of convergence of Fourier coefficients, and in terms of convergence in distribution modulo 1, for a random variable to be digit-regular (significant-digit regular), and basic relationships between digit-regularity and various classical classes of probability measures and normal numbers are given. These results provide a theoretical basis for analyses of roundoff errors in numerical algorithms which use floating-point arithmetic, and for detection of fraud in numerical data via using goodness-of-fit of the least significant digits to uniform, complementing recent tests for leading significant digits based on Benford's law.normal numbers, significant digits, Benford's law, digit-regular random variable, significant-digit-regular random variable, law of least significant digits, floating-point numbers, nonleading digits, trailing digits

Design and implementation of high-radix arithmetic systems based on the SDNR/RNS data representation

This project involved the design and implementation of high-radix arithmetic systems based on the hybrid SDNRIRNS data representation. Some real-time applications require a real-time arithmetic system. An SDNR/RNS arithmetic system provides parallel, real-time processing. The advantages and disadvantages of high-radix SDNR/RNS arithmetic, and the feasibility of implementing SDNR/RNS arithmetic systems in CMOS VLSI technology, were investigated in this project. A common methodological model, which included the stages of analysis, design, implementation, testing, and simulation, was followed. The combination of the SDNR and RNS transforms potential complex logic networks into simpler logic blocks. It was found that when constructing a SDNRIRNS adder, factors such as the radix, digit set, and moduli must be taken into account. There are many avenues still to explore. For example, implementing other arithmetic systems in the same CMOS VLSI technology used in this project and comparing them to equivalent SDNR/RNS systems would provide a set of benchmarks. These benchmarks would be useful in addressing issues relating to relative performance