FPGA implementation of Reed Solomon codec for 40Gbps Forward Error Correction in optical networks

Reed-Solomon error correcting codes (RS codes) are widely used in communication and data storage systems to recover data from possible errors that occur during data transfer. A growing application of RS codes is Forward Error Correction (FEC) in the Optical Network (OTN G.709), which uses RS(255,239) to support the OTU-3 (43.018 Gbps) standard. There have been considerable efforts in the area of RS architecture for ASIC implementation. However, there appears to be little reported work on efficient RS codec (encoder and decoder) for Field Programmable Gate Arrays (FPGAs), which has increasing interests in industry. This thesis investigates the implementation and design methodology of the RS(255,239) codec on FPGAs. A portable VHDL code is developed and synthesized for Xilinx\u27s Virtex4 and Altera\u27s StratixII. The FPGA architectures are analyzed and the required design methodologies are adopted to efficiently utilize the available resources. Unfortunately, due to the fixed size of FPGA devices, the RS decoder is not only constrained by the required timing of the system, but also by the size of the targeted device. This research will facilitate the decision-making process for selecting a reconfigurable device for a RS decoder, implementing the Berlekamp-Massey Algorithm

High Speed S-band Communications System for Nanosatellites

3Cat-3 is a nanosatellite based on the 6 unit cubesat standard. Its payload is an optical multispectral imager that imposes stringent downlink requirements for a nanosatellite. This TFG is based on the experience gained in 3Cat-1 and 3Cat-2 communications systems to develop a "high speed" (goal >= 5 Mbps) downlink for nanosatellites based on the TI CC3200.In order to accomplish the objectives of the next generation of nanosatellites high-speed downlinks have to be designed. This goal faces stringent design constraints as nanosatellites are limit in power, processing capabilities and dimensions. In the quest for higher bit rates the widely used VHF band has to be replaced for higher frequency bands and the link budged margin tightened, decreasing the SNR at reception. The proposed solution uses COTS 2.4 GHz WiFi adapters as transceivers. Range limitations imposed by the default 802.11 mode of operation are bypassed by using packet forging and injection at transmission jointly with monitor mode at reception. A loss-resilient unidirectional downlink is achieved by using application-layer encoding by means of LPDC-Staircase codes. This solution has been already implemented in 3CAT-2, a 6 unit cubesat GNSS-R mission to be launched in July 2016. In addition, bursts of errors are combated by using Reed-Solomon. The system has been tested under Doppler shift and scintillation effects, and a 188Km link between Barcelona and Mallorca has been performed, showing satisfactory results

Recent Results on the Implementation of a Burst Error and Burst Erasure Channel Emulator Using an FPGA Architecture

The behaviour of a transmission channel may be simulated using the performance abilities of current generation multiprocessing hardware, namely, a multicore Central Processing Unit (CPU), a general purpose Graphics Processing Unit (GPU), or a Field Programmable Gate Array (FPGA). These were investigated by Cullinan et al. in a recent paper (published in 2012) where these three devices capabilities were compared to determine which device would be best suited towards which specific task. In particular, it was shown that, for the application which is objective of our work (i.e., for a transmission channel simulation), the FPGA is 26.67 times faster than the GPU and 10.76 times faster than the CPU. Motivated by these results, in this paper we propose and present a direct hardware emulation. In particular, a Cyclone II FPGA architecture is implemented to simulate a burst error channel behaviour, in which errors are clustered together, and a burst erasure channel behaviour, in which the erasures are clustered together. The results presented in the paper are valid for any FPGA architecture that may be considered for this scope

SoftCast: Clean-slate Scalable Wireless Video

Video broadcast and mobile video challenge the conventional wireless design. In broadcast and mobile scenarios the bit rate supported by the channel differs across receivers and varies quickly over time. The conventional design however forces the source to pick a single bit rate and degrades sharply when the channel cannot not support the chosen bit rate. This paper presents SoftCast, a clean-slate design for wireless video where the source transmits one video stream that each receiver decodes to a video quality commensurate with its specific instantaneous channel quality. To do so, SoftCast ensures the samples of the digital video signal transmitted on the channel are linearly related to the pixels' luminance. Thus, when channel noise perturbs the transmitted signal samples, the perturbation naturally translates into approximation in the original video pixels. Hence, a receiver with a good channel (low noise) obtains a high fidelity video, and a receiver with a bad channel (high noise) obtains a low fidelity video. We implement SoftCast using the GNURadio software and the USRP platform. Results from a 20-node testbed show that SoftCast improves the average video quality (i.e., PSNR) across broadcast receivers in our testbed by up to 5.5dB. Even for a single receiver, it eliminates video glitches caused by mobility and increases robustness to packet loss by an order of magnitude

SoftCast

The focus of this demonstration is the performance of streaming video over the mobile wireless channel. We compare two schemes: the standard approach to video which transmits H.264/AVC-encoded stream over 802.11-like PHY, and SoftCast -- a clean-slate design for wireless video where the source transmits one video stream that each receiver decodes to a video quality commensurate with its specific instantaneous channel quality

Real-time transmission of digital video using variable-length coding

Huffman coding is a variable-length lossless compression technique where data with a high probability of occurrence is represented with short codewords, while 'not-so-likely' data is assigned longer codewords. Compression is achieved when the high-probability levels occur so frequently that their benefit outweighs any penalty paid when a less likely input occurs. One instance where Huffman coding is extremely effective occurs when data is highly predictable and differential coding can be applied (as with a digital video signal). For that reason, it is desirable to apply this compression technique to digital video transmission; however, special care must be taken in order to implement a communication protocol utilizing Huffman coding. This paper addresses several of the issues relating to the real-time transmission of Huffman-coded digital video over a constant-rate serial channel. Topics discussed include data rate conversion (from variable to a fixed rate), efficient data buffering, channel coding, recovery from communication errors, decoder synchronization, and decoder architectures. A description of the hardware developed to execute Huffman coding and serial transmission is also included. Although this paper focuses on matters relating to Huffman-coded digital video, the techniques discussed can easily be generalized for a variety of applications which require transmission of variable-length data

Techniques for ubiquitous reliable data storage

This portfolio thesis documents the work undertaken by the author under the auspices of the Engineering Doctorate (EngD) programme. The research work undertaken was completed at the sponsoring company, A2E Limited. There is a wide range of products and solutions to meet both commercial and personal electronic storage needs. This work documents research and development over a four year period into algorithms, implementations and product development for novel storage solutions for commercial and personal use. The design work and technical and business objectives were guided by the sponsoring company, A4E limited. This portfolio thesis considers the storage market at the start of the project, the commercial and technical aspects relevant to this market place and describes the development and testing of a RAID 6 algorithm in both hardware and software. The key contributions presented in this portfolio thesis include the implementation of the smallest and fastest FPGA based Reed-Solomon RAID 6 hardware accelerator. We also present the first commercial implementation of a Reed-Solomon RAID 6 intellectual property (IP) block. Both the hardware and software implementation are discussed in detail along with the supporting IP blocks and device drivers. Documentation of the product development stages and additional project work carried out to provide an understanding of product development stages and the requirements placed during such work are also examined. the results of testing and implementation are considered and the performance of the proposed solution is considered along with the commercial viability and success of the project

Accurate modelling of Ka-band videoconferencing systems based on the quality of experience

This work formed part of the project TWISTER, which was financially supported under the European Union 6th Framework Programme (FP6). The authors are solely responsible for the contents of the paper, which does not represent the opinion of the European Commission.Ka-band satellite multimedia communication networks play important roles because of their capability to provide the required bandwidth in remote places of the globe. However, because of design complexity, in practice they suffer from poor design and performance degradation because of being practically forced to guarantee acceptable end-user satisfaction in conditions of extremely low bit error rates, which is emphasised with the vulnerability of compressed video content to transmission errors, often impossible to be applied during the service development phase. A novel discrete event simulation model is presented, which provides performance estimation for such systems based on subjective measurement and a better quality of experience. The authors show that the proposed model reduces implementation cost and is flexible to be used for different network topologies around the globe.peer-reviewe