Energetics of hydrogen impurities in aluminum and their effect on mechanical properties

The effects of hydrogen impurities in the bulk and on the surface of aluminum are theoretically investigated. Within the framework of density functional theory, we have obtained the dependence on H concentration of the stacking fault energy, the cleavage energy, the Al/H surface energy and the Al/H/Al interface formation energy. The results indicate a strong dependence of the slip energy barrier in the $[\bar 211]$ direction the cleavage energy in the [111] direction and the Al/H/Al interface formation energy, on H concentration and on tension. The dependence of the Al/H surface energy on H coverage is less pronounced, while the optimal H coverage is $\leq 0.25$ monolayer. The calculated activation energy for diffusion between high symmetry sites in the bulk and on the surface is practically the same, 0.167 eV. From these results, we draw conclusions about the possible effect of H impurities on mechanical properties, and in particular on their role in embrittlement of Al.Comment: 9 pages, 5 figure

DeSyRe: on-Demand System Reliability

The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect and fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints

The Art of Fault Injection

Classical greek philosopher considered the foremost virtues to be temperance, justice, courage, and prudence. In this paper we relate these cardinal virtues to the correct methodological approaches that researchers should follow when setting up a fault injection experiment. With this work we try to understand where the "straightforward pathway" lies, in order to highlight those common methodological errors that deeply influence the coherency and the meaningfulness of fault injection experiments. Fault injection is like an art, where the success of the experiments depends on a very delicate balance between modeling, creativity, statistics, and patience

Testing microelectronic biofluidic systems

According to the 2005 International Technology Roadmap for Semiconductors, the integration of emerging nondigital CMOS technologies will require radically different test methods, posing a major challenge for designers and test engineers. One such technology is microelectronic fluidic (MEF) arrays, which have rapidly gained importance in many biological, pharmaceutical, and industrial applications. The advantages of these systems, such as operation speed, use of very small amounts of liquid, on-board droplet detection, signal conditioning, and vast digital signal processing, make them very promising. However, testable design of these devices in a mass-production environment is still in its infancy, hampering their low-cost introduction to the market. This article describes analog and digital MEF design and testing method

Layout level design for testability strategy applied to a CMOS cell library

The layout level design for testability (LLDFT) rules used here allow to avoid some hard to detect faults or even undetectable faults on a cell library by modifying the cell layout without changing their behavior and achieving a good level of reliability. These rules avoid some open faults or reduce their appearance probability. The main purpose has been to apply that set of LLDFT rules on the cells of the library designed at the Centre Nacional de Microelectronica (CNM) in order to obtain a highly testable cell library. The authors summarize the main results (area overhead and performance degradation) of the application of the LLDFT rules on the cell

Resilient Pathways to Atomic Attachment of Quantum Dot Dimers and Artificial Solids from Faceted CdSe Quantum Dot Building Blocks.

The goal of this work is to identify favored pathways for preparation of defect-resilient attached wurtzite CdX (X = S, Se, Te) nanocrystals. We seek guidelines for oriented attachment of faceted nanocrystals that are most likely to yield pairs of nanocrystals with either few or no electronic defects or electronic defects that are in and of themselves desirable and stable. Using a combination of in situ high-resolution transmission electron microscopy (HRTEM) and electronic structure calculations, we evaluate the relative merits of atomic attachment of wurtzite CdSe nanocrystals on the {11̅00} or {112̅0} family of facets. Pairwise attachment on either facet can lead to perfect interfaces, provided the nanocrystal facets are perfectly flat and the angles between the nanocrystals can adjust during the assembly. Considering defective attachment, we observe for {11̅00} facet attachment that only one type of edge dislocation forms, creating deep hole traps. For {112̅0} facet attachment, we observe that four distinct types of extended defects form, some of which lead to deep hole traps whereas others only to shallow hole traps. HRTEM movies of the dislocation dynamics show that dislocations at {11̅00} interfaces can be removed, albeit slowly. Whereas only some extended defects at {112̅0} interfaces could be removed, others were trapped at the interface. Based on these insights, we identify the most resilient pathways to atomic attachment of pairs of wurtzite CdX nanocrystals and consider how these insights can translate to the creation of electronically useful materials from quantum dots with other crystal structures

Scan Test Coverage Improvement Via Automatic Test Pattern Generation (Atpg) Tool Configuration

The scan test coverage improvement by using automatic test pattern generation (ATPG) tool configuration was investigated. Improving the test coverage is essential in detecting manufacturing defects in semiconductor industry so that high quality products can be supplied to consumers. The ATPG tool used was Mentor Graphics Tessent TestKompress (version 2014.1). The study was done by setting up a few experiments of utilizing and modifying ATPG commands and switches, observing the test coverage improvement from the statistical reports provided during pattern generation process and providing relatable discussions. By modifying the ATPG commands, it can be expected to have some improvement in the test coverage. The scan test patterns generated were stuck-at test patterns. Based on the experiments done, comparison was made on the different coverage readings and the most optimized method and flow of ATPG were determined. The most optimized flow gave an improvement of 0.91% in test coverage which is acceptable since this method does not involve a change in design. The test patterns generated were converted and tested using automatic test equipment (ATE) to observe its performance on real silicon. The test coverage improvement using ATPG tool instead of the design-based method is important as a faster workaround for back-end engineers to provide high quality test contents in such a short product development duration