Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications

As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well

Scintillator Pad Detector: Very Front End Electronics

El Laboratori d'Altes Energies de La Salle és un membre d'un grup acreditat per la Generalitat. Aquest grup està format per part del Departament d'Estructura i Constituents de la Matèria de la Facultat de Física de la Universitat de Barcelona, part del departament d'Electrònica de la mateixa Facultat i pel grup de La Salle. Tots ells estan involucrats en el disseny d'un subdetector en l'experiment de LHCb del CERN: el SPD (Scintillator Pad Detector). El SPD és part del Calorímetre de LHCb. Aquest sistema proporciona possibles hadrons d'alta energia, electrons i fotons pel primer nivell de trigger. El SPD està format per una làmina centellejeadora de plàstic, dividida en 600 cel.les de diferent tamany per obtenir una millor granularitat aprop del feix. Les partícules carregades que travessin el centellejador generaran una ionització del mateix, a diferència dels fotons que no la ionitzaran. Aquesta ionització, generarà un pols de llum que serà recollit per una WLS que està enrotllada dins de les cel.les centellejadores. La llum serà transmesa al sistema de lectura mitjançant fibres clares. Per reducció de costos, aquestes 6000 cel.les estan dividides en grups, usant MAPMT (fotomultiplicadors multiànode) de 64 canals per rebre la informació en el sistema de lectura. El senyal de sortida dels fotomultilplicadors és irregular degut al baix nivell de fotoestadística, uns 20-30 fotoelectrons per MIP, i degut també a la resposta de la fibra WLS, que té un temps de baixada lent. Degut a tot això, el processat del senyal, es realitza primer durant la integració de la càrrega total i finalment per la correcció de la cua que conté el senyal provinent del PMT. Aquesta Tesi està enfocada en el sistema de lectura de l'electrònica del VFE del SPD. Aquest, està format per un ASIC (dissenyat pel grup de la UB) encarregat d'integrar el senyal, compensar el senyal restant i comparar el nivell d'energia obtingut amb un llindar programable (fa la distinció entre electrons i fotons), una FPGA que programa aquests llindars i compensacions de cada ASIC i fa el mapeig de cada canal rebut en el detector i finalment usa serialitzadors LVDS per enviar la informació de sortida al trigger de primer nivell. En el disseny d'aquest tipus d'electrònica s'haurà de tenir en compte, per un costat, restriccions de tipus mecànic: l'espai disponible per l'electrònica és limitat i escàs, i per un altre costat, el nivell de radiació que deurà suportar és considerable i s'haurà de comprobar que tots els components superin un cert test de radiació, i finalment, també s'haurà de tenir en compte la distància que separa els VFE dels racks on la informació és enviada i el tipus de senyal amb el que es treballa en aquest tipus d'experiments: mixta i de poc rang.El Laboratorio de Altas Energías de la Salle es un miembro de un grupo acreditado por La Generalitat. Este grupo está formado por parte del departamento de Estructura i Constituents de la Matèria de la Facultad de Física de la Universidad de Barcelona, parte del departamento de Electrónica de la misma Facultad y el grupo de La Salle. Todos ellos están involucrados en el diseño de un subdetector en el experimento de LHCb del CERN: El SPD (Scintillator Pad Detector). El SPD es parte del Calorímetro de LHCb. Este sistema proporciona posibles hadrones de alta energía, electrones y fotones para el primer nivel de trigger.El SPD está diseñado para distinguir entre electrones y fotones para el trigger de primer nivel. Este detector está formado por una lámina centelleadora de plástico, dividida en 6000 celdas de diferente tamaño para obtener una mejor granularidad cerca del haz. Las partículas cargadas que atraviesen el centelleador generarán una ionización del mismo, a diferencia de los fotones que no la generarán. Esta ionización generará, a su vez, un pulso de luz que será recogido por una WLS que está enrollada dentro de las celdas centelleadoras. La luz será transmitida al sistema de lectura mediante fibras claras. Para reducción de costes, estas 6000 celdas están divididas en grupos, utilizando un MAPMT (fotomultiplicadores multiánodo) de 64 canales para recibir la información en el sistema de lectura. La señal de salida de los fotomultiplicadores es irregular debido al bajo nivel de fotoestadística, unos 20-30 fotoelectrones por MIP, y debido también a la respuesta de la fibra WLS, que tiene un tiempo de bajada lento. Debido a todo esto, el procesado de la señal, se realiza primero mediante la integración de la carga total y finalmente por la substracción de la señal restante fuera del período de integración. Esta Tesis está enfocada en el sistema de lectura de la electrónica del VFE del SPD. Éste, está formado por un ASIC (diseñado por el grupo de la UB) encargado de integrar la señal, compensar la señal restante y comparar el nivel de energía obtenido con un umbral programable (que distingue entre electrones y fotones), y una FPGA que programa estos umbrales y compensaciones de cada ASIC, y mapea cada uno de los canales recibidos en el detector y finalmente usa serializadores LVDS para enviar la información de salida al trigger de primer nivel. En el diseño de este tipo de electrónica se deberá tener en cuenta, por un lado, restricciones del tipo mecánico: el espacio disponible para la electrónica en sí, es limitado y escaso, por otro lado, el nivel de radiación que deberá soportar es considerable y se tendrá que comprobar que todos los componentes usado superen un cierto test de radiación, y finalmente, también se deberá tener en cuenta la distancia que separa los VFE de los racks dónde la información es enviada y el tipo de señal con el que se trabaja en este tipo de experimentos: mixta y de poco rango.Laboratory in La Salle is a member of a Credited Research Group by La Generatitat. This group is formed by a part of the ECM department, a part of the Electronics department at UB (University of Barcelona) and La Salle's group. Together, they are involved in the design of a subdetector at LHCb Experiment at CERN: the SPD (Scintillator Pad Detector). The SPD is a part of LHCb Calorimeter. That system provides high energy hadrons, electron and photons candidates for the first level trigger. The SPD is designed to distinguish electrons and photons for this first level trigger. This detector is a plastic scintillator layer, divided in about 6000 cells of different size to obtain better granularity near the beam. Charged particles will produce, and photons will not, ionisation on the scintillator. This ionisation generates a light pulse that is collected by a Wavelength Shifting (WLS) fibre that is twisted inside the scintillator cell. The light is transmitted through a clear fibre to the readout system. For cost reduction, these 6000 cells are divided in groups using a MAPMT of 64 channels for receiving information in the readout system. The signal outing the SPD PMTs is rather unpredictable as a result of the low number of photostatistics, 20-30 photoelectrons per MIP, and the due to the response of the WLS fibre, which has low decay time. Then, the signal processing must be performed by first integrating the total charge and later subtracting to avoid pile-up. This PhD is focused on the VFE (Very Front End) of SPD Readout system. It is performed by a specific ASIC (designed by the UB group) which integrates the signal, makes the pile-up compensation, and compares the level obtained to a programmable threshold (distinguishing electrons and photons), an FPGA which programs the ASIC thresholds, pile-up subtraction and mapping the channels in the detector and finally LVDS serializers, in order to send information to the first level trigger system. Not only mechanical constraints had to be taken into account in the design of the card as a result of the little space for the readout electronics but also, on one hand, the radiation quote expected in the environment and on the other hand, the distance between the VFE electronics and the racks were information is sent and the signal range that this kind of experiments usually have

Novel Multicarrier Memory Channel Architecture Using Microwave Interconnects: Alleviating the Memory Wall

abstract: The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon. A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel. Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Next generation >200 Gb/s multicore fiber short-reach networks employing machine learning

This work proposes and evaluates the use of machine learning (ML) techniques on >200 Gb/s short-reach systems employing weakly coupled multicore fiber (MCF) and Kramers-Kronig (KK) receivers. The short-reach systems commonly found in intra data centers (DC) connections demand low cost-efficient direct detection receivers (DD). The KK receivers allow the combination of higher modulation order, such as 16-QAM used in coherent systems, with the low complexity and low cost of DD. Thus, the use of KK receivers allows to increase the bit rate and spectral efficiency while maintaining the cost of DD systems as this is an important requirement in DC. The use of MCF allows to increase the system capacity as well as the system cable density, although the use of MCF induces additional distortion, known as inter-core crosstalk (ICXT), to the system. Thus, low complexity ML techniques such as k-means clustering, k nearest neighbor (KNN) and artificial neural network (ANN) (estimation feedforward neural network (FNN) and classification feedforward neural network) are proposed to mitigate the effects of random ICXT. The performance improvement provided by the k-means clustering, KNN and the two types of FNN techniques is assessed and compared with the system performance obtained without the use of ML. The use of estimation and classification FNN prove to significantly improve the system performance by mitigating the impact of the ICXT on the received signal. This is achieved by employing only 10 neurons in the hidden layer and four input features. It has been shown that k-means or KNN techniques do not provide performance improvement compared to the system without using ML. These conclusions are valid for direct detection MCF-based short-reach systems with the product between the skew (relative time delay between cores) and the symbol rate much lower than one (skew x symbol rate « 1). By employing the proposed ANNs, the system shows an improvement of approximately 12 dB on the ICXT level, for the same outage probability when comparing with the system without the use of ML. For the BER threshold of 10−1.8 and compared with the standard system operating without employing ML techniques, the system operating with the proposed ANNs show a received optical power improvement of almost 3 dB and a ICXT level improvement of approximately 9 dB when the mean BER is analized.Este trabalho propõe e avalia o uso de técnicas de machine learning (ML) em sistemas de curto alcance com ritmo binário superior a 200 Gb/s utilizando receptores Kramers-Kronig (KK) e fibras multinúcleo (MCF). Os sistemas de curto alcance usualmente encontrados em conexões intra-data centers (DC) exigem receptores de deteção direta (DD) de baixo custo. Os receptores KK permitem a combinação de sistemas de modulação de maior ordem, tais como o 16-QAM, usado em sistemas coerentes, com o baixo custo dos receptores DD. Portanto, o uso de receptores KK permite melhorar o ritmo binário e eficiência espectral e manter a eficiência de custo dos sistemas DD, o que é importante em DC. O uso de fibras multinúcleo permite o aumento da capacidade do sistema, bem como a densidade de cabos. No entanto, o uso de MCF introduz uma distorção adicional no sistema conhecida como inter-core crosstalk (ICXT). Para mitigar os efeitos do ICXT aleatório, são propostas e avaliadas técnicas de ML de baixa complexidade como k-means clustering, k nearest neighbor (KNN) e rede neuronais artificiais (ANN). O desempenho associado à utilização de algoritmos de ML (k-means, KNN e duas redes neuronais do tipo feedforward (FNN): uma para estimação e outra para classificação), é avaliado e comparado com o desempenho do sistema obtido sem o uso de ML. A utilização de FNN para estimação e classificação conduziram a uma melhoria significativa no desempenho do sistema, mitigando o impacto do ICXT no sinal recebido. Isso é alcançado com o uso de uma rede neuronal com uma arquitetura muito simples contendo quatro entradas e 10 neurónios na camada escondida. Foi demonstrado que os algoritmos k-means e KNN não proporcionam melhoria de desempenho em comparação com o sistema sem o uso de ML. Essas conclusões são válidas para sistemas DD de curto alcance baseados em MCF com o produto entre o skew (atraso relativo entre os núcleos) e o ritmo de símbolos muito menor que um (skew x symbol rate « 1). Com o uso das ANNs, o sistema apresenta uma melhoria de aproximadamente 12 dB na probabilidade de indisponibilidade quando comparado com o sistema sem o uso de ML. Para o limite de BER de 10−1.8 , e comparado com o sistema padrão sem o uso de técnicas de ML, o sistema com o uso de ANN mostra uma melhoria na potência óptica recebida de quase 3 dB e uma melhoria no nível de ICXT de aproximadamente 9 dB em relação ao BER médio

Short-reach 200 Gb/s SDM network employing direct-detection and optical SSBI mitigation

In order to respond to the growing capacity demands of next-generation optical networks, this dissertation proposes an innovative transmission scheme for direct-detection (DD) multi-core fibre (MCF) short-reach networks with one core dedicated to carriers transmission and the remaining cores dedicated to signals transmission. With this scheme, a low-complexity signal-signal beat interference (SSBI) mitigation approach can be employed. This may be of particular interest for systems requiring electronic chromatic dispersion (CD) compensation at the receiver side. The performance of a 200 Gb/s polar non-return-to-zero (NRZ) signal in a MCF short-reach network employing the proposed transmission scheme impaired by CD and the combined effect of the skew and the laser phase noise is evaluated through numerical simulation. The results show that systems employing lasers with broader linewidths become more sensitive to the skew, limiting further the system performance due to phase-tointensity conversion. When CD is not compensated, employing the SSBI mitigation technique enables distances up to 180 m, showing potential to be implemented in intra data centre networks. These results are obtained when the signal mean optical power is 18 dB higher than the carrier mean optical power, and when the SSBI estimation is not corrupted by electrical noise. Nevertheless, the higher potential of the proposed transmission scheme may be achieved for systems in which the CD effect is compensated electronically at the receiver side. For systems with full CD compensation, the results show a significant performance improvement obtained by the SSBI mitigation approach employed.De modo a responder às crescentes exigências de capacidade das redes óticas de próxima geração, nesta dissertação propõe-se um esquema inovador de transmissão para redes de curto alcance baseado em deteção-direta (DD) e fibras multinúcleo (MCF), com um núcleo dedicado à transmissão de portadoras e os restantes núcleos dedicados à transmissão dos sinais. Com este esquema, pode ser implementada uma abordagem de mitigação da interferência do batimento sinal-sinal (SSBI) de baixa complexidade. Isto pode ser de particular interesse para sistemas que requerem compensação eletrónica da dispersão cromática (CD) no lado do recetor. O desempenho de um sinal NRZ polar de 200 Gb/s numa rede MCF de curto alcance utilizando o esquema de transmissão proposto limitado pela CD e pelo efeito combinado do atraso relativo de propagação (skew) e do ruído de fase do laser é avaliado através de simulação numérica. Os resultados mostram que os sistemas que utilizam lasers com maiores larguras de linha tornam-se mais vulneráveis ao skew, limitando mais o desempenho do sistema devido à conversão do ruído de fase em intensidade. Quando a CD não é compensada, a utilização da técnica de mitigação da SSBI permite distâncias até 180 m, mostrando potencial para ser implementada dentro de centros de dados. Estes resultados são obtidos quando a potência ótica média do sinal é 18 dB superior à potência ótica média da portadora, e quando a estimação da SSBI não é corrompida pelo ruído elétrico. No entanto, o potencial mais elevado do esquema de transmissão proposto poderá ser alcançado para sistemas em que o efeito da CD é compensado eletronicamente no lado do recetor. Para sistemas com compensação total de CD, os resultados mostram uma melhoria significativa do desempenho obtida pela abordagem de mitigação da SSBI implementada

High-Speed and Low-Energy On-Chip Communication Circuits.

Continuous technology scaling sharply reduces transistor delays, while fixed-length global wire delays have increased due to less wiring pitch with higher resistance and coupling capacitance. Due to this ever growing gap, long on-chip interconnects pose well-known latency, bandwidth, and energy challenges to high-performance VLSI systems. Repeaters effectively mitigate wire RC effects but do little to improve their energy costs. Moreover, the increased complexity and high level of integration requires higher wire densities, worsening crosstalk noise and power consumption of conventionally repeated interconnects. Such increasing concerns in global on-chip wires motivate circuits to improve wire performance and energy while reducing the number of repeaters. This work presents circuit techniques and investigation for high-performance and energy-efficient on-chip communication in the aspects of encoding, data compression, self-timed current injection, signal pre-emphasis, low-swing signaling, and technology mapping. The improved bus designs also consider the constraints of robust operation and performance/energy gains across process corners and design space. Measurement results from 5mm links on 65nm and 90nm prototype chips validate 2.5-3X improvement in energy-delay product.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/75800/1/jseo_1.pd