3,554 research outputs found
VLSI Implementation of Low Power Reconfigurable MIMO Detector
Multiple Input Multiple Output (MIMO) systems are a key technology for next
generation high speed wireless communication standards like 802.11n, WiMax etc.
MIMO enables spatial multiplexing to increase channel bandwidth which requires the
use of multiple antennas in the receiver and transmitter side. The increase in bandwidth
comes at the cost of high silicon complexity of MIMO detectors which result, due to the
intricate algorithms required for the separation of these spatially multiplexed streams.
Previous implementations of MIMO detector have mainly dealt with the issue of
complexity reduction, latency minimization and throughput enhancement. Although,
these detectors have successfully mapped algorithms to relatively simpler circuits but
still, latency and throughput of these systems need further improvements to meet
standard requirements. Additionally, most of these implementations don’t deal with the
requirements of reconfigurability of the detector to multiple modulation schemes and
different antennae configurations. This necessary requirement provides another
dimension to the implementation of MIMO detector and adds to the implementation
complexity.
This thesis focuses on the efficient VLSI implementation of the MIMO detector
with an emphasis on performance and re-configurability to different modulation
schemes. MIMO decoding in our detector is based on the fixed sphere decoding
algorithm which has been simplified for an effective VLSI implementation without
considerably degrading the near optimal bit error rate performance. The regularity of the
architecture makes it suitable for a highly parallel and pipelined implementation. The
decoder has intrinsic traits for dynamic re-configurability to different modulation and
encoding schemes. This detector architecture can be easily tuned for high/low
performance requirements with slight degradation/improvement in Bit Error Rate (BER)
depending on needs of the overlying application. Additionally, various architectural
optimizations like pipelining, parallel processing, hardware scheduling, dynamic voltage
and frequency scaling have been explored to improve the performance, energy
requirements and re-configurability of the design
On Low-Resolution ADCs in Practical 5G Millimeter-Wave Massive MIMO Systems
Nowadays, millimeter-wave (mmWave) massive multiple-input multiple-output
(MIMO) systems is a favorable candidate for the fifth generation (5G) cellular
systems. However, a key challenge is the high power consumption imposed by its
numerous radio frequency (RF) chains, which may be mitigated by opting for
low-resolution analog-to-digital converters (ADCs), whilst tolerating a
moderate performance loss. In this article, we discuss several important issues
based on the most recent research on mmWave massive MIMO systems relying on
low-resolution ADCs. We discuss the key transceiver design challenges including
channel estimation, signal detector, channel information feedback and transmit
precoding. Furthermore, we introduce a mixed-ADC architecture as an alternative
technique of improving the overall system performance. Finally, the associated
challenges and potential implementations of the practical 5G mmWave massive
MIMO system {with ADC quantizers} are discussed.Comment: to appear in IEEE Communications Magazin
Large-Scale MIMO Detection for 3GPP LTE: Algorithms and FPGA Implementations
Large-scale (or massive) multiple-input multiple-output (MIMO) is expected to
be one of the key technologies in next-generation multi-user cellular systems,
based on the upcoming 3GPP LTE Release 12 standard, for example. In this work,
we propose - to the best of our knowledge - the first VLSI design enabling
high-throughput data detection in single-carrier frequency-division multiple
access (SC-FDMA)-based large-scale MIMO systems. We propose a new approximate
matrix inversion algorithm relying on a Neumann series expansion, which
substantially reduces the complexity of linear data detection. We analyze the
associated error, and we compare its performance and complexity to those of an
exact linear detector. We present corresponding VLSI architectures, which
perform exact and approximate soft-output detection for large-scale MIMO
systems with various antenna/user configurations. Reference implementation
results for a Xilinx Virtex-7 XC7VX980T FPGA show that our designs are able to
achieve more than 600 Mb/s for a 128 antenna, 8 user 3GPP LTE-based large-scale
MIMO system. We finally provide a performance/complexity trade-off comparison
using the presented FPGA designs, which reveals that the detector circuit of
choice is determined by the ratio between BS antennas and users, as well as the
desired error-rate performance.Comment: To appear in the IEEE Journal of Selected Topics in Signal Processin
Efficient DSP and Circuit Architectures for Massive MIMO: State-of-the-Art and Future Directions
Massive MIMO is a compelling wireless access concept that relies on the use
of an excess number of base-station antennas, relative to the number of active
terminals. This technology is a main component of 5G New Radio (NR) and
addresses all important requirements of future wireless standards: a great
capacity increase, the support of many simultaneous users, and improvement in
energy efficiency. Massive MIMO requires the simultaneous processing of signals
from many antenna chains, and computational operations on large matrices. The
complexity of the digital processing has been viewed as a fundamental obstacle
to the feasibility of Massive MIMO in the past. Recent advances on
system-algorithm-hardware co-design have led to extremely energy-efficient
implementations. These exploit opportunities in deeply-scaled silicon
technologies and perform partly distributed processing to cope with the
bottlenecks encountered in the interconnection of many signals. For example,
prototype ASIC implementations have demonstrated zero-forcing precoding in real
time at a 55 mW power consumption (20 MHz bandwidth, 128 antennas, multiplexing
of 8 terminals). Coarse and even error-prone digital processing in the antenna
paths permits a reduction of consumption with a factor of 2 to 5. This article
summarizes the fundamental technical contributions to efficient digital signal
processing for Massive MIMO. The opportunities and constraints on operating on
low-complexity RF and analog hardware chains are clarified. It illustrates how
terminals can benefit from improved energy efficiency. The status of technology
and real-life prototypes discussed. Open challenges and directions for future
research are suggested.Comment: submitted to IEEE transactions on signal processin
- …