1,493 research outputs found

    Advanced digital modulation: Communication techniques and monolithic GaAs technology

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    Communications theory and practice are merged with state-of-the-art technology in IC fabrication, especially monolithic GaAs technology, to examine the general feasibility of a number of advanced technology digital transmission systems. Satellite-channel models with (1) superior throughput, perhaps 2 Gbps; (2) attractive weight and cost; and (3) high RF power and spectrum efficiency are discussed. Transmission techniques possessing reasonably simple architectures capable of monolithic fabrication at high speeds were surveyed. This included a review of amplitude/phase shift keying (APSK) techniques and the continuous-phase-modulation (CPM) methods, of which MSK represents the simplest case

    Low-Voltage GaN Based Inverter for Power Steering Application

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    In the paper, an experimental evaluation of a low voltage Gallium Nitride (GaN) based inverter suitable for power steering application is presented. The inverter switches belong to the last generation of low voltage enhancement-mode normally-off GaN Field-Effect Transistor (FET). The main advantage in the usage of these devices is the high switching frequency capability with consequently volume reduction of the passive components. On the other hand, the layout and the device packaging solution are a challenge to reduce the parasitic inductances. Furthermore, the dv/dt increasing with the switching frequency need a deep investigation in a motor drive application. The paper deals with the advances and drawbacks of the GaN FETs in two-level Pulse Width Modulation (PWM) motor drive applications providing a piece of detailed experimental evidence and design guidelines

    Development of a Supercapacitor based Surge Resistant Uninterruptible Power Supply

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    Uninterruptible Power Supplies (UPSs) provide short-term power back-up to sensitive electronic and electrical equipments, where an unexpected power loss could lead to undesirable outcomes. They usually bridge the connected equipment between the utility mains power and other long term back-up power systems like generators. A UPS also provides a “clean” source of power, meaning they filter the connected equipment from distortions in electrical parameters of the mains power like noise, harmonics, surges, sags and spikes. A surge resistant UPS or SRUPS is one that has the capability to withstand surges, which are momentary or sustained increases in the mains voltage, and react quickly enough to offer protection to the connected equipment from the same. Usually UPSs run off battery power when the utility mains power is absent. But the SRUPS developed in this design project uses super capacitors instead of battery packs. The reason for this is that the high energy-densities and medium power-densities offered by super capacitors allow for it to serve two purposes. One is to provide the DC power to operate the UPS in the absence of mains power, as an alternative to batteries. Secondly, super capacitors can withstand heavy momentary high current/voltage surges due to its high energy-density characteristics. Also as the life-time of super capacitors is much higher than that of conventional batteries and as they do not need regular topping-up or inspection, the end result is a truly maintenance-free UPS. Most commercial UPSs do not have inherent surge protection capabilities. The UPS is one entity while a discrete surge protection module is inserted between the utility mains and the UPS to provide for transient surge suppression. In the proposed SRUPS, the super capacitor, because of their inherent capability to absorb transient surges, forms a protective front end to the actual UPS rather than needing to have the involvement of discrete protection devices

    Power quality and electromagnetic compatibility: special report, session 2

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    The scope of Session 2 (S2) has been defined as follows by the Session Advisory Group and the Technical Committee: Power Quality (PQ), with the more general concept of electromagnetic compatibility (EMC) and with some related safety problems in electricity distribution systems. Special focus is put on voltage continuity (supply reliability, problem of outages) and voltage quality (voltage level, flicker, unbalance, harmonics). This session will also look at electromagnetic compatibility (mains frequency to 150 kHz), electromagnetic interferences and electric and magnetic fields issues. Also addressed in this session are electrical safety and immunity concerns (lightning issues, step, touch and transferred voltages). The aim of this special report is to present a synthesis of the present concerns in PQ&EMC, based on all selected papers of session 2 and related papers from other sessions, (152 papers in total). The report is divided in the following 4 blocks: Block 1: Electric and Magnetic Fields, EMC, Earthing systems Block 2: Harmonics Block 3: Voltage Variation Block 4: Power Quality Monitoring Two Round Tables will be organised: - Power quality and EMC in the Future Grid (CIGRE/CIRED WG C4.24, RT 13) - Reliability Benchmarking - why we should do it? What should be done in future? (RT 15

    Energy Storage as Enabling Technology for Smart Grid

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    Awareness about human impact on mighty climatic changes is radically changing our concept of energy. The thoughtless use of energy slowly leaves our habits and good use of energy is certain the way of a better future. CO2 emission reduction and carbon fossil fuel limitation are the main targets of governmental actions: this is possible thanks to technology improvement as efficient generation from renewable sources and good management of the electricity network. In recent years distributed generation, also of small size, grew up causing new management problems, indeed production from renewable energy sources (RES) is intermittent and unprogrammable. Energy storage systems can be a solution to these problems and pave the way to completely active users, grid parity and smart grid, moreover can be an useful tool to increase electricity access in rural areas. Research on energy storage is intrinsically a multidisciplinary field: storage types, power stages, technologies, topologies, weather, forecast, control algorithms, regulatory, safety and business cases to mention the most importants. In the present work is described the whole design of an energy storage system. First chapters are dedicated to a description of energy storage context, chapters 1 and 2; indeed, it is a matter of fact that in the last years, energy storage became more and more interesting from explicit mention as a tool against climatic changes to first options on the market. The general approach was the realization of a modular energy storage system for residential application, hardware and software design steps are deeply described in chapters 3 and 4. Simulations and tests on the prototype are reported in chapter 5. Finally conclusion and future works are given. At the end of the document some appendices are included to cover specific aspects touched during the work thesis

    Characterization Methodology, Modeling, and Converter Design for 600 V Enhancement-Mode GaN FETs

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    Gallium Nitride (GaN) power devices are an emerging technology that have only become available commercially in the past few years. This new technology enables the design of converters at higher frequencies and efficiencies than those achievable with conventional Si devices. This dissertation reviews the unique characteristics, commercial status, and design challenges that surround GaN FETs, in order to provide sufficient background to potential GaN-based converter designers.Methodology for experimentally characterizing a GaN FET was also presented, including static characterization with a curve tracer and impedance analyzer, as well as dynamic characterization in a double pulse test setup. This methodology was supplemented by additional tests to determine losses caused by Miller-induced cross talk, and the tradeoff between these losses and overlap losses was studied for one example device.Based on analysis of characterization results, a simplified model was developed to describe the overall switching behavior and some unique features of the device. The impact of the Miller effect during the turn-on transient was studied, as well as the dynamic performance of GaN at elevated temperature.Furthermore, solutions were proposed for several key design challenges in GaN-based converters. First, a driver-integrated overcurrent and short-circuit protection scheme was developed, based on the relationship between gate voltage and drain current in GaN gate injection transistors. Second, the limitations on maximum utilization of current and voltage in a GaN FET were studied, particularly the voltage overshoots following turn-on and turn-off switching transients, and the effective cooling of GaN FETs in higher power operation. A thermal design was developed for heat extraction from bottom-cooled surface-mount devices. These solutions were verified in a GaN-based full-bridge single-phase inverter

    Review and Characterization of Gallium Nitride Power Devices

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    Gallium Nitride (GaN) power devices are an emerging technology that have only recently become available commercially. This new technology enables the design of converters at higher frequencies and efficiencies than those achievable with conventional Si devices. This thesis reviews the characteristics and commercial status of both vertical and lateral GaN power devices from the user perspective, providing the background necessary to understand the significance of these recent developments. Additionally, the challenges encountered in GaN-based converter design are considered, such as the consequences of faster switching on gate driver design and board layout. Other issues include the unique reverse conduction behavior, dynamic on-resistance, breakdown mechanisms, thermal design, device availability, and reliability qualification. Static and dynamic characterization was then performed across the full current, voltage, and temperature range of this device to enable effective GaN-based converter design. Static testing was performed with a curve tracer and precision impedance analyzer. A double pulse test setup was constructed and used to measure switching loss and time at the fastest achievable switching speed, and the subsequent overvoltages due to the fast switching were characterized. The results were also analyzed to characterize the effects of cross-talk in the active and synchronous devices of a phase-leg topology with enhancement-mode GaN HFETs. Based on these results and analysis, an accurate loss model was developed for the device under test. Based on analysis of these characterization results, a simplified model was developed to describe the overall switching behavior and some unique features of the device. The consequences of the Miller effect during the turn-on transient were studied to show that no Miller plateau occurs, but rather a decreased gate voltage slope, followed by a sharp drop. The significance of this distinction is derived and explained. GaN performance at elevated temperature was also studied, because turn-on time increases significantly with temperature, and turn-on losses increase as a result. Based on this relationship, a temperature-dependent turn-on model and a linear scaling factor was proposed for estimating turn-on loss in e-mode GaN HFETs

    Robust Design of Variation-Sensitive Digital Circuits

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    The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to 12 GHz, and a single chip will contain over 12 billion transistors in 2020, as given by the International Technology Roadmap for Semiconductors (ITRS) initiative. ITRS also predicts that the scaling of CMOS devices and process technology, as it is known today, will become much more difficult as the industry advances towards the 16nm technology node and further. This aggressive scaling of CMOS technology has pushed the devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as process variations, radiation induced soft errors, and aging degradation mechanisms. These new design challenges have a strong impact on the parametric yield of nanometer digital circuits and also result in functional yield losses in variation-sensitive digital circuits such as Static Random Access Memory (SRAM) and flip-flops. Moreover, sub-threshold SRAM and flip-flops circuits, which are aggravated by the strong demand for lower power consumption, show larger sensitivity to these challenges which reduces their robustness and yield. Accordingly, it is not surprising that the ITRS considers variability and reliability as the most challenging obstacles for nanometer digital circuits robust design. Soft errors are considered one of the main reliability and robustness concerns in SRAM arrays in sub-100nm technologies due to low operating voltage, small node capacitance, and high packing density. The SRAM arrays soft errors immunity is also affected by process variations. We develop statistical design-oriented soft errors immunity variations models for super-threshold and sub-threshold SRAM cells accounting for die-to-die variations and within-die variations. This work provides new design insights and highlights the important design knobs that can be used to reduce the SRAM cells soft errors immunity variations. The developed models are scalable, bias dependent, and only require the knowledge of easily measurable parameters. This makes them useful in early design exploration, circuit optimization as well as technology prediction. The derived models are verified using Monte Carlo SPICE simulations, referring to an industrial hardware-calibrated 65nm CMOS technology. The demand for higher performance leads to very deep pipelining which means that hundreds of thousands of flip-flops are required to control the data flow under strict timing constraints. A violation of the timing constraints at a flip-flop can result in latching incorrect data causing the overall system to malfunction. In addition, the flip-flops power dissipation represents a considerable fraction of the total power dissipation. Sub-threshold flip-flops are considered the most energy efficient solution for low power applications in which, performance is of secondary importance. Accordingly, statistical gate sizing is conducted to different flip-flops topologies for timing yield improvement of super-threshold flip-flops and power yield improvement of sub-threshold flip-flops. Following that, a comparative analysis between these flip-flops topologies considering the required overhead for yield improvement is performed. This comparative analysis provides useful recommendations that help flip-flops designers on selecting the best flip-flops topology that satisfies their system specifications while taking the process variations impact and robustness requirements into account. Adaptive Body Bias (ABB) allows the tuning of the transistor threshold voltage, Vt, by controlling the transistor body voltage. A forward body bias reduces Vt, increasing the device speed at the expense of increased leakage power. Alternatively, a reverse body bias increases Vt, reducing the leakage power but slowing the device. Therefore, the impact of process variations is mitigated by speeding up slow and less leaky devices or slowing down devices that are fast and highly leaky. Practically, the implementation of the ABB is desirable to bias each device in a design independently, to mitigate within-die variations. However, supplying so many separate voltages inside a die results in a large area overhead. On the other hand, using the same body bias for all devices on the same die limits its capability to compensate for within-die variations. Thus, the granularity level of the ABB scheme is a trade-off between the within-die variations compensation capability and the associated area overhead. This work introduces new ABB circuits that exhibit lower area overhead by a factor of 143X than that of previous ABB circuits. In addition, these ABB circuits are resolution free since no digital-to-analog converters or analog-to-digital converters are required on their implementations. These ABB circuits are adopted to high performance critical paths, emulating a real microprocessor architecture, for process variations compensation and also adopted to SRAM arrays, for Negative Bias Temperature Instability (NBTI) aging and process variations compensation. The effectiveness of the new ABB circuits is verified by post layout simulation results and test chip measurements using triple-well 65nm CMOS technology. The highly capacitive nodes of wide fan-in dynamic circuits and SRAM bitlines limit the performance of these circuits. In addition, process variations mitigation by statistical gate sizing increases this capacitance further and fails in achieving the target yield improvement. We propose new negative capacitance circuits that reduce the overall parasitic capacitance of these highly capacitive nodes. These negative capacitance circuits are adopted to wide fan-in dynamic circuits for timing yield improvement up to 99.87% and to SRAM arrays for read access yield improvement up to 100%. The area and power overheads of these new negative capacitance circuits are amortized over the large die area of the microprocessor and the SRAM array. The effectiveness of the new negative capacitance circuits is verified by post layout simulation results and test chip measurements using 65nm CMOS technology
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