An Automated Design-flow for FPGA-based Sequential Simulation

In this paper we describe the automated design flow that will transform and map a given homogeneous or heterogeneous hardware design into an FPGA that performs a cycle accurate simulation. The flow replaces the required manually performed transformation and can be embedded in existing standard synthesis flows. Compared to the earlier manually translated designs, this automated flow resulted in a reduced number of FPGA hardware resources and higher simulation frequencies. The implementation of the complete design flow is work in progress.\u

The review of heterogeneous design frameworks/Platforms for digital systems embedded in FPGAs and SoCs

Systems-on-a-chip integrate specialized modules to provide well-defined functionality. In order to guarantee its efficiency, designersare careful to choose high-level electronic components. In particular,FPGAs (field-programmable gate array) have demonstrated theirability to meet the requirements of emerging technology. However,traditional design methods cannot keep up with the speed andefficiency imposed by the embedded systems industry, so severalframeworks have been developed to simplify the design process of anelectronic system, from its modeling to its physical implementation.This paper illustrates some of them and presents a comparative studybetween them. Indeed, we have selected design methods of SoC(ESP4ML and HLS4ML, OpenESP, LiteX, RubyRTL, PyMTL,SysPy, PyRTL, DSSoC) and NoC networks on OCN chip (PyOCN)and in general on FPGA (PRGA, OpenFPGA, AnyHLS, PYNQ, andPyLog).The objective of this article is to analyze each tool at several levelsand to discuss the benefit of each in the scientific community. Wewill analyze several aspects constituting the architecture and thestructure of the platforms to make a comparative study of thehardware and software design flows of digital systems.

Experimental Investigation and Evaluation of Future Active Distribution Networks

The UK government’s policy to achieve a 20% renewable energy generation target by 2020, will require significant amounts of SSEG (Small-Scale Embedded Generation) to be connected. In addition to the expected economic and environmental benefits, the anticipated growth in SSEG brings with it numerous challenges for the operation of low voltage and medium voltage distribution networks. At present, there are a number of competing active network management concepts being considered to overcome these challenges and at Durham University a concept defined as the Small Scale Energy Zone (SSEZ) has been proposed and is investigated as part of this research. To further this, a bespoke active low voltage distribution network emulator known as the Experimental SSEZ has been developed by the author. Controllable emulated SSEG, controllable energy storage and controllable emulated load are incorporated into this laboratory. A transformation system has been developed to relate the operation of this system to that of low voltage distribution networks. Centralised and distributed network control systems have been developed for the Experimental SSEZ. These systems were used to evaluate, in conjunction with the relevant literature, the implementation of similar systems on future low voltage distribution networks. Both centralised and distributed control system architectures were found to have their merits. This research should therefore be useful in informing design decisions when developing and implementing active distribution network management systems on LV networks