91 research outputs found
A PUF based Lightweight Hardware Security Architecture for IoT
With an increasing number of hand-held electronics, gadgets, and other smart devices, data is present in a large number of platforms, thereby increasing the risk of security, privacy, and safety breach than ever before. Due to the extreme lightweight nature of these devices, commonly referred to as IoT or `Internet of Things\u27, providing any kind of security is prohibitive due to high overhead associated with any traditional and mathematically robust cryptographic techniques. Therefore, researchers have searched for alternative intuitive solutions for such devices. Hardware security, unlike traditional cryptography, can provide unique device-specific security solutions with little overhead, address vulnerability in hardware and, therefore, are attractive in this domain. As Moore\u27s law is almost at its end, different emerging devices are being explored more by researchers as they present opportunities to build better application-specific devices along with their challenges compared to CMOS technology. In this work, we have proposed emerging nanotechnology-based hardware security as a security solution for resource constrained IoT domain. Specifically, we have built two hardware security primitives i.e. physical unclonable function (PUF) and true random number generator (TRNG) and used these components as part of a security protocol proposed in this work as well. Both PUF and TRNG are built from metal-oxide memristors, an emerging nanoscale device and are generally lightweight compared to their CMOS counterparts in terms of area, power, and delay. Design challenges associated with designing these hardware security primitives and with memristive devices are properly addressed. Finally, a complete security protocol is proposed where all of these different pieces come together to provide a practical, robust, and device-specific security for resource-limited IoT systems
Circuit Techniques for Low-Power and Secure Internet-of-Things Systems
The coming of Internet of Things (IoT) is expected to connect the physical world to the cyber world through ubiquitous sensors, actuators and computers. The nature of these applications demand long battery life and strong data security. To connect billions of things in the world, the hardware platform for IoT systems must be optimized towards low power consumption, high energy efficiency and low cost. With these constraints, the security of IoT systems become a even more difficult problem compared to that of computer systems. A new holistic system design considering both hardware and software implementations is demanded to face these new challenges.
In this work, highly robust and low-cost true random number generators (TRNGs) and physically unclonable functions (PUFs) are designed and implemented as security primitives for secret key management in IoT systems. They provide three critical functions for crypto systems including runtime secret key generation, secure key storage and lightweight device authentication. To achieve robustness and simplicity, the concept of frequency collapse in multi-mode oscillator is proposed, which can effectively amplify the desired random variable in CMOS devices (i.e. process variation or noise) and provide a runtime monitor of the output quality. A TRNG with self-tuning loop to achieve robust operation across -40 to 120 degree Celsius and 0.6 to 1V variations, a TRNG that can be fully synthesized with only standard cells and commercial placement and routing tools, and a PUF with runtime filtering to achieve robust authentication, are designed based upon this concept and verified in several CMOS technology nodes. In addition, a 2-transistor sub-threshold amplifier based "weak" PUF is also presented for chip identification and key storage. This PUF achieves state-of-the-art 1.65% native unstable bit, 1.5fJ per bit energy efficiency, and 3.16% flipping bits across -40 to 120 degree Celsius range at the same time, while occupying only 553 feature size square area in 180nm CMOS.
Secondly, the potential security threats of hardware Trojan is investigated and a new Trojan attack using analog behavior of digital processors is proposed as the first stealthy and controllable fabrication-time hardware attack. Hardware Trojan is an emerging concern about globalization of semiconductor supply chain, which can result in catastrophic attacks that are extremely difficult to find and protect against. Hardware Trojans proposed in previous works are based on either design-time code injection to hardware description language or fabrication-time modification of processing steps. There have been defenses developed for both types of attacks. A third type of attack that combines the benefits of logical stealthy and controllability in design-time attacks and physical "invisibility" is proposed in this work that crosses the analog and digital domains. The attack eludes activation by a diverse set of benchmarks and evades known defenses.
Lastly, in addition to security-related circuits, physical sensors are also studied as fundamental building blocks of IoT systems in this work. Temperature sensing is one of the most desired functions for a wide range of IoT applications. A sub-threshold oscillator based digital temperature sensor utilizing the exponential temperature dependence of sub-threshold current is proposed and implemented. In 180nm CMOS, it achieves 0.22/0.19K inaccuracy and 73mK noise-limited resolution with only 8865 square micrometer additional area and 75nW extra power consumption to an existing IoT system.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138779/1/kaiyuan_1.pd
Contributions on using embedded memory circuits as physically unclonable functions considering reliability issues
[eng] Moving towards Internet-of-Things (IoT) era, hardware security becomes a crucial
research topic, because of the growing demand of electronic products that are remotely
connected through networks. Novel hardware security primitives based on
manufacturing process variability are proposed to enhance the security of the IoT
systems. As a trusted root that provides physical randomness, a physically unclonable
function is an essential base for hardware security.
SRAM devices are becoming one of the most promising alternatives for the
implementation of embedded physical unclonable functions as the start-up value of
each bit-cell depends largely on the variability related with the manufacturing process.
Not all bit-cells experience the same degree of variability, so it is possible that some cells
randomly modify their logical starting value, while others will start-up always at the
same value. However, physically unclonable function applications, such as identification
and key generation, require more constant logical starting value to assure high reliability
in PUF response. For this reason, some kind of post-processing is needed to correct the
errors in the PUF response.
Unfortunately, those cells that have more constant logic output are difficult to be
detected in advance. This work characterizes by simulation the start-up value
reproducibility proposing several metrics suitable for reliability estimation during design
phases. The aim is to be able to predict by simulation the percentage of cells that will be
suitable to be used as PUF generators. We evaluate the metrics results and analyze the
start-up values reproducibility considering different external perturbation sources like several power supply ramp up times, previous internal values in the bit-cell, and
different temperature scenarios. The characterization metrics can be exploited to
estimate the number of suitable SRAM cells for use in PUF implementations that can be
expected from a specific SRAM design.[cat] En lâera de la Internet de les coses (IoT), garantir la seguretat del hardware ha
esdevingut un tema de recerca crucial, en especial a causa de la creixent demanda de
productes electrĂČnics que es connecten remotament a travĂ©s de xarxes. Per millorar la
seguretat dels sistemes IoT, sâhan proposat noves solucions hardware basades en la
variabilitat dels processos de fabricaciĂł. Les funcions fĂsicament inclonables (PUF)
constitueixen una font fiable dâaleatorietat fĂsica i sĂłn una base essencial per a la
seguretat hardware.
Les memĂČries SRAM sâestan convertint en una de les alternatives mĂ©s prometedores per
a la implementaciĂł de funcions fĂsicament inclonables encastades. AixĂČ Ă©s aixĂ ja que el
valor dâencesa de cada una de les cel·les que formen els bits de la memĂČria depĂšn en
gran mesura de la variabilitat prĂČpia del procĂ©s de fabricaciĂł. No tots els bits tenen el
mateix grau de variabilitat, aixĂ que algunes cel·les canvien el seu estat lĂČgic dâencesa de
forma aleatĂČria entre enceses, mentre que dâaltres sempre assoleixen el mateix valor
en totes les enceses. No obstant aixĂČ, les funcions fĂsicament inclonables, que sâutilitzen
per generar claus dâidentificaciĂł, requereixen un valor lĂČgic dâencesa constant per tal
dâassegurar una resposta fiable del PUF. Per aquest motiu, normalment es necessita
algun tipus de postprocessament per corregir els possibles errors presents en la resposta
del PUF. Malauradament, les cel·les que presenten una resposta més constant són
difĂcils de detectar a priori.
Aquest treball caracteritza per simulaciĂł la reproductibilitat del valor dâencesa de cel·les
SRAM, i proposa diverses mĂštriques per estimar la fiabilitat de les cel·les durant les fases de disseny de la memĂČria. L'objectiu Ă©s ser capaç de predir per simulaciĂł el percentatge
de cel·les que seran adequades per ser utilitzades com PUF. Sâavaluen els resultats de
diverses mĂštriques i sâanalitza la reproductibilitat dels valors dâencesa de les cel·les
considerant diverses fonts de pertorbacions externes, com diferents rampes de tensiĂł
per a lâencesa, els valors interns emmagatzemats prĂšviament en les cel·les, i diferents
temperatures. Es proposa utilitzar aquestes mÚtriques per estimar el nombre de cel·les
SRAM adients per ser implementades com a PUF en un disseny dâSRAM especĂfic.[spa] En la era de la Internet de las cosas (IoT), garantizar la seguridad del hardware se ha
convertido en un tema de investigaciĂłn crucial, en especial a causa de la creciente
demanda de productos electrónicos que se conectan remotamente a través de redes.
Para mejorar la seguridad de los sistemas IoT, se han propuesto nuevas soluciones
hardware basadas en la variabilidad de los procesos de fabricaciĂłn. Las funciones
fĂsicamente inclonables (PUF) constituyen una fuente fiable de aleatoriedad fĂsica y son
una base esencial para la seguridad hardware.
Las memorias SRAM se estĂĄn convirtiendo en una de las alternativas mĂĄs prometedoras
para la implementaciĂłn de funciones fĂsicamente inclonables empotradas. Esto es asĂ,
puesto que el valor de encendido de cada una de las celdas que forman los bits de la
memoria depende en gran medida de la variabilidad propia del proceso de fabricaciĂłn.
No todos los bits tienen el mismo grado de variabilidad. AsĂ pues, algunas celdas cambian
su estado lĂłgico de encendido de forma aleatoria entre encendidos, mientras que otras
siempre adquieren el mismo valor en todos los encendidos. Sin embargo, las funciones
fĂsicamente inclonables, que se utilizan para generar claves de identificaciĂłn, requieren
un valor lĂłgico de encendido constante para asegurar una respuesta fiable del PUF. Por
este motivo, normalmente se necesita algĂșn tipo de posprocesado para corregir los
posibles errores presentes en la respuesta del PUF. Desafortunadamente, las celdas que
presentan una respuesta mĂĄs constante son difĂciles de detectar a priori.
Este trabajo caracteriza por simulaciĂłn la reproductibilidad del valor de encendido de
celdas SRAM, y propone varias métricas para estimar la fiabilidad de las celdas durante las fases de diseño de la memoria. El objetivo es ser capaz de predecir por simulación el
porcentaje de celdas que serĂĄn adecuadas para ser utilizadas como PUF. Se evalĂșan los
resultados de varias métricas y se analiza la reproductibilidad de los valores de
encendido de las celdas considerando varias fuentes de perturbaciones externas, como
diferentes rampas de tensiĂłn para el encendido, los valores internos almacenados
previamente en las celdas, y diferentes temperaturas. Se propone utilizar estas métricas
para estimar el nĂșmero de celdas SRAM adecuadas para ser implementadas como PUF
en un diseño de SRAM especĂfico
D2.1 - Report on Selected TRNG and PUF Principles
This report represents the final version of Deliverable 2.1 of the HECTOR work package WP2. It is a result of discussions and work on Task 2.1 of all HECTOR partners involved in WP2. The aim of the Deliverable 2.1 is to select principles of random number generators (RNGs) and physical unclonable functions (PUFs) that fulfill strict technology, design and security criteria. For example, the selected RNGs must be suitable for implementation in logic devices according to the German AIS20/31 standard. Correspondingly, the selected PUFs must be suitable for applying similar security approach. A standard PUF evaluation approach does not exist, yet, but it should be proposed in the framework of the project. Selected RNGs and PUFs should be then thoroughly evaluated from the point of view of security and the most suitable principles should be implemented in logic devices, such as Field Programmable Logic Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs) during the next phases of the project
Design of hardware-based security solutions for interconnected systems
Among all the different research lines related to hardware security, there is a particular topic
that strikingly attracts attention. That topic is the research regarding the so-called Physical
Unclonable Functions (PUF). The PUFs, as can be seen throughout the Thesis, present the
novel idea of connecting digital values uniquely to a physical entity, just as human biometrics
does, but with electronic devices. This beautiful idea is not free of obstacles, and is the core
of this Thesis. It is studied from different angles in order to better understand, in particular,
SRAM PUFs, and to be able to integrate them into complex systems that expand their
potential.
During Chapter 1, the PUFs, their properties and their main characteristics are defined. In
addition, the different types of PUFs, and their main applications in the field of security are
also summarized.
Once we know what a PUF is, and the types of them we can find, throughout Chapter 2
an exhaustive analysis of the SRAM PUFs is carried out, given the wide availability of
SRAMs today in most electronic circuits (which dramatically reduces the cost of deploying
any solution). An algorithm is proposed to improve the characteristics of SRAM PUFs, both
to generate identifiers and to generate random numbers, simultaneously. The results of this
Chapter demonstrates the feasibility of implementing the algorithm, so in the following
Chapters it is explored its integration in both hardware and software systems.
In Chapter 3 the hardware design and integration of the algorithm introduced in Chapter 2
is described. The design is presented together with some examples of use that demonstrate
the possible practical realizations in VLSI designs.
In an analogous way, in Chapter 4 the software design and integration of the algorithm
introduced in Chapter 2 is described. The design is presented together with some examples
of use that demonstrate the possible practical realizations in low-power IoT devices. The
algorithm is also described as part of a secure firmware update protocol that has been
designed to be resistant to most current attacks, ensuring the integrity and trustworthiness of
the updated firmware.In Chapter 5, following the integration of PUF-based solutions into protocols, PUFs
are used as part of an authentication protocol that uses zero-knowledge proofs. The cryptographic
protocol is a Lattice-based post-quantum protocol that guarantees the integrity and
anonymity of the identity generated by the PUF. This type of architecture prevents any type of
impersonation or virtual copy of the PUF, since this is unknown and never leaves the device.
Specifically, this type of design has been carried out with the aim of having traceability of
identities without ever knowing the identity behind, which is very interesting for blockchain
technologies.
Finally, in Chapter 6 a new type of PUF, named as BPUF (Behavioral and Physical Unclonable
Function), is proposed and analyzed according to the definitions given in Chapter 1.
This new type of PUF significantly changes the metrics and concepts to which we were
used to in previous Chapters. A new multi-modal authentication protocol is presented in this
Chapter, taking advantage of the challenge-response tuples of BPUFs. An example of BPUFs
is illustrated with SRAMs.
A proposal to integrate the BPUFs described in Chapter 6 into the protocol of Chapter 5,
as well as the final remarks of the Thesis, can be found in Chapter 7
Maximum-likelihood decoding of device-specific multi-bit symbols for reliable key generation
We present a PUF key generation scheme that uses the provably optimal method of maximum-likelihood (ML) detection on symbols derived from PUF response bits. Each device forms a noisy, device-specific symbol constellation, based on manufacturing variation. Each detected symbol is a letter in a codeword of an error correction code, resulting in non-binary codewords. We present a three-pronged validation strategy: i. mathematical (deriving an optimal symbol decoder), ii. simulation (comparing against prior approaches), and iii. empirical (using implementation data). We present simulation results demonstrating that for a given PUF noise level and block size (an estimate of helper data size), our new symbol-based ML approach can have orders of magnitude better bit error rates compared to prior schemes such as block coding, repetition coding, and threshold-based pattern matching, especially under high levels of noise due to extreme environmental variation. We demonstrate environmental reliability of a ML symbol-based soft-decision error correction approach in 28nm FPGA silicon, covering -65°C to 105°C ambient (and including 125°C junction), and with 128bit key regeneration error probability †1 ppm.Bavaria California Technology Center (Grant 2014-1/9
A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors
With the continued success of the open RISC-V architecture, practical deployment of RISC-V processors necessitates an in-depth consideration of their testability, safety and security aspects. This survey provides an overview of recent developments in this quickly-evolving field. We start with discussing the application of state-of-the-art functional and system-level test solutions to RISC-V processors. Then, we discuss the use of RISC-V processors for safety-related applications; to this end, we outline the essential techniques necessary to obtain safety both in the functional and in the timing domain and review recent processor designs with safety features. Finally, we survey the different aspects of security with respect to RISC-V implementations and discuss the relationship between cryptographic protocols and primitives on the one hand and the RISC-V processor architecture and hardware implementation on the other. We also comment on the role of a RISC-V processor for system security and its resilience against side-channel attacks
Design and Implementation of Low Power SRAM Using Highly Effective Lever Shifters
The explosive growth of battery-operated devices has made low-power design a priority in recent years. In high-performance Systems-on-Chip, leakage power consumption has become comparable to the dynamic component, and its relevance increases as technology scales. These trends are even more evident for SRAM memory devices since they are a dominant source of standby power consumption in low-power application processors. The on-die SRAM power consumption is particularly important for increasingly pervasive mobile and handheld applications where battery life is a key design and technology attribute. In the SRAM-memory design, SRAM cells also comprise the most significant portion of the total chip. Moreover, the increasing number of transistors in the SRAM memories and the MOSs\u27 increasing leakage current in the scaled technologies have turned the SRAM unit into a power-hungry block for both dynamic and static viewpoints. Although the scaling of the supply voltage enables low-power consumption, the SRAM cells\u27 data stability becomes a major concern. Thus, the reduction of SRAM leakage power has become a critical research concern.
To address the leakage power consumption in high-performance cache memories, a stream of novel integrated circuit and architectural level techniques are proposed by researchers including leakage-current management techniques, cell array leakage reduction techniques, bitline leakage reduction techniques, and leakage current compensation techniques. The main goal of this work was to improve the cell array leakage reduction techniques in order to minimize the leakage power for SRAM memory design in low-power applications.
This study performs the body biasing application to reduce leakage current as well. To adjust the NMOSs\u27 threshold voltage and consequently leakage current, a negative DC voltage could be applied to their body terminal as a second gate. As a result, in order to generate a negative DC voltage, this study proposes a negative voltage reference that includes a trimming circuit and a negative level shifter. These enhancements are employed to a 10kb SRAM memory operating at 0.3V in a 65nm CMOS process
Modélisation et caractérisation des fonctions non clonables physiquement
Physically Unclonable Functions, or PUFs, are innovative technologies devoted to solve some security and identification issues. Similarly to a human fingerprint, PUFs allows to identify uniquely electronic devices as they produce an instance-specific signature. Applications as authentication or key generation can take advantage of this embedded function. The main property that we try to obtain from a PUF is the generation of a unique response that varies randomly from one physical device to another without allowing its prediction. Another important property of these PUF is to always reproduce the same response for the same input challenge even in a changing environment. Moreover, the PUF system should be secure against attacks that could reveal its response. In this thesis, we are interested in silicon PUF which take advantage of inherent process variations during the manufacturing of CMOS integrated circuits. We present several PUF constructions, discuss their properties and the implementation techniques to use them in security applications. We first present two novel PUF structures. The first one, called âLoop PUFâ is a delay based PUF which relies on the comparison of delay measurements of identical serial delay chains. The major contribution brought by the use of this structure is its implementation simplicity on both ASIC and FPGA platforms, and its flexibility as it can be used for reliable authentication or key generation. The second proposed structure is a ring-oscillator based PUF cells âTERO PUFâ. It exploits the oscillatory metastability of cross-coupled elements, and can also be used as True Random Number Generator (TRNG). More precisely, the PUF response takes advantage from the introduced oscillatory metastability of an SR flip-flop when the S and R inputs are connected to the same input signal. Experimental results show the high performance of these two proposed PUF structures. Second, in order to fairly compare the quality of different delay based PUFs, we propose a specific characterization method. It is based on statistical measurements on basic delay elements. The main benefit of this method is that it allows the designer to be sure that the PUF will meet the expected performances before its implementation and fabrication. Finally, Based on the unclonability and unpredictability properties of the PUFs, we present new techniques to perform âloop PUFâ authentication and cryptographic key generation. Theoretical and experimental results show the efficiency of the introduced techniques in terms of complexity and reliabilityLes fonctions non clonables physiquement, appelĂ©es PUF (Physically Unclonable Functions), reprĂ©sentent une technologie innovante qui permet de rĂ©soudre certains problĂšmes de sĂ©curitĂ© et dâidentification. Comme pour les empreintes humaines, les PUF permettent de diffĂ©rencier des circuits Ă©lectroniques car chaque exemplaire produit une signature unique. Ces fonctions peuvent ĂȘtre utilisĂ©es pour des applications telles que lâauthentification et la gĂ©nĂ©ration de clĂ©s cryptographiques. La propriĂ©tĂ© principale que lâon cherche Ă obtenir avec les PUF est la gĂ©nĂ©ration dâune rĂ©ponse unique qui varie de façon alĂ©atoire dâun circuit Ă un autre, sans la possibilitĂ© de la prĂ©dire. Une autre propriĂ©tĂ© de ces PUF est de toujours reproduire, quel que soit la variation de lâenvironnement de test, la mĂȘme rĂ©ponse Ă un mĂȘme dĂ©fi dâentrĂ©e. En plus, une fonction PUF doit ĂȘtre sĂ©curisĂ©e contre les attaques qui permettraient de rĂ©vĂ©ler sa rĂ©ponse. Dans cette thĂšse, nous nous intĂ©ressons aux PUF en silicium profitant des variations inhĂ©rentes aux technologies de fabrication des circuits intĂ©grĂ©s CMOS. Nous prĂ©sentons les principales architectures de PUF, leurs propriĂ©tĂ©s, et les techniques mises en Ćuvre pour les utiliser dans des applications de sĂ©curitĂ©. Nous prĂ©sentons dâabord deux nouvelles structures de PUF. La premiĂšre structure appelĂ©e âLoop PUFâ est basĂ©e sur des chaĂźnes dâĂ©lĂ©ments Ă retard contrĂŽlĂ©s. Elle consiste Ă comparer les dĂ©lais de chaĂźnes Ă retard identiques qui sont mises en sĂ©rie. Les points forts de cette structure sont la facilitĂ© de sa mise en Ćuvre sur les deux plates-formes ASIC et FPGA, la grande flexibilitĂ© pour lâauthentification des circuits intĂ©grĂ©s ainsi que la gĂ©nĂ©ration de clĂ©s de chiffrement. La deuxiĂšme structure proposĂ©e âTERO PUFâ est basĂ©e sur le principe de cellules temporairement oscillantes. Elle exploite la mĂ©tastabilitĂ© oscillatoire dâĂ©lĂ©ments couplĂ©s en croix, et peut aussi ĂȘtre utilisĂ©e pour un gĂ©nĂ©rateur vrai dâalĂ©as (TRNG). Plus prĂ©cisĂ©ment, la rĂ©ponse du PUF profite de la mĂ©tastabilitĂ© oscillatoire introduite par une bascule SR lorsque les deux entrĂ©es S et R sont connectĂ©es au mĂȘme signal dâentrĂ©e. Les rĂ©sultats expĂ©rimentaux montrent le niveau de performances Ă©levĂ© des deux structures de PUF proposĂ©es. Ensuite, afin de comparer Ă©quitablement la qualitĂ© des diffĂ©rentes PUF Ă retard, nous proposons une mĂ©thode de caractĂ©risation spĂ©cifique. Elle est basĂ©e sur des mesures statistiques des Ă©lĂ©ments Ă retard. Le principal avantage de cette mĂ©thode vient de sa capacitĂ© Ă permettre au concepteur dâĂȘtre sĂ»r que la fonction PUF aura les performances attendues avant sa mise en Ćuvre et sa fabrication. Enfin, en se basant sur les propriĂ©tĂ©s de non clonabilitĂ© et de lâimprĂ©visibilitĂ© des PUF, nous prĂ©sentons de nouvelles techniques dâauthentification et de gĂ©nĂ©ration de clĂ©s de chiffrement en utilisant la âloop PUFâ proposĂ©e. Les rĂ©sultats thĂ©oriques et expĂ©rimentaux montrent lâefficacitĂ© des techniques introduites en termes de complexitĂ© et de fiabilit
- âŠ