Intelligent approaches to VLSI routing

Very Large Scale Integrated-circuit (VLSI) routing involves many large-size and complex problems and most of them have been shown to be NP-hard or NP-complete. As a result, conventional approaches, which have been successfully used to handle relatively small-size routing problems, are not suitable to be used in tackling large-size routing problems because they lead to \u27combinatorial explosion\u27 in search space. Hence, there is a need for exploring more efficient routing approaches to be incorporated into today\u27s VLSI routing system. This thesis strives to use intelligent approaches, including symbolic intelligence and computational intelligence, to solve three VLSI routing problems: Three-Dimensional (3-D) Shortest Path Connection, Switchbox Routing and Constrained Via Minimization. The 3-D shortest path connection is a fundamental problem in VLSI routing. It aims to connect two terminals of a net that are distributed in a 3-D routing space subject to technological constraints and performance requirements. Aiming at increasing computation speed and decreasing storage space requirements, we present a new A* algorithm for the 3-D shortest path connection problem in this thesis. This new A*algorithm uses an economical representation and adopts a novel back- trace technique. It is shown that this algorithm can guarantee to find a path if one exists and the path found is the shortest one. In addition, its computation speed is fast, especially when routed nets are spare. The computational complexities of this A* algorithm at the best case and the worst case are O(Ɩ) and 0(Ɩ3), respectively, where Ɩ is the shortest path length between the two terminals. Most importantly, this A\u27 algorithm is superior to other shortest path connection algorithms as it is economical in terms of storage space requirement, i.e., 1 bit/grid. The switchbox routing problem aims to connect terminals at regular intervals on the four sides of a rectangle routing region. From a computational point of view, the problem is NP-hard. Furthermore, it is extremely complicated and as the consequence no existing algorithm can guarantee to find a solution even if one exists no matter how high the complexity of the algorithm is. Previous approaches to the switch box routing problem can be divided into algorithmic approaches and knowledge-based approaches. The algorithmic approaches are efficient in computational time, but they are unsucessful at achieving high routing completion rate, especially for some dense and complicated switchbox routing problems. On the other hand, the knowledge-based approaches can achieve high routing completion rate, but they are not efficient in computation speed. In this thesis we present a hybrid approach to the switchbox routing problem. This hybrid approach is based on a new knowledge-based routing technique, namely synchronized routing, and combines some efficient algorithmic routing techniques. Experimental results show it can achieve the high routing completion rate of the knowledge-based approaches and the high efficiency of the algorithmic approaches. The constrained via minimization is an important optimization problem in VLSI routing. Its objective is to minimize the number of vias introduced in VLSI routing. From computational perspective, the constrained via minimization is NP-complete. Although for a special case where the number of wire segments splits at a via candidate is not more than three, elegant theoretical results have been obtained. For a general case in which there exist more than three wire segment splits at a via candidate few approaches have been proposed, and those approaches are only suitable for tackling some particular routing styles and are difficult or impossible to adjust to meet practical requirements. In this thesis we propose a new graph-theoretic model, namely switching graph model, for the constrained via minimization problem. The switching graph model can represent both grid-based and grid less routing problems, and allows arbitrary wire segments split at a via candidate. Then on the basis of the model, we present the first genetic algorithm for the constrained via minimization problem. This genetic algorithm can tackle various kinds of routing styles and be configured to meet practical constraints. Experimental results show that the genetic algorithm can find the optimal solutions for most cases in reasonable time

Performance Driven Global Routing Through Gradual Refinement

We propose a heuristic for VLSI interconnect global routing that can optimize routing congestion, delay and number of bends, which are often competing objectives. Routing flexibilities under timing constraints are obtained and exploited to reduce congestion subject to timing constraints. The wire routes are determined through gradual refinement according to probabilistic estimation on congestions so that the congestion is minimized while the number of bends on wires is limited. The experiments on both random generated circuits and benchmark circuits confirm the effectiveness of this method

A complete design path for the layout of flexible macros

XIV+172hlm.;24c

AI/ML Algorithms and Applications in VLSI Design and Technology

An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations

Design automation and analysis of three-dimensional integrated circuits

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (p. 165-176).This dissertation concerns the design of circuits and systems for an emerging technology known as three-dimensional integration. By stacking individual components, dice, or whole wafers using a high-density electromechanical interconnect, three-dimensional integration can achieve scalability and performance exceeding that of conventional fabrication technologies. There are two main contributions of this thesis. The first is a computer-aided design flow for the digital components of a three-dimensional integrated circuit (3-D IC). This flow primarily consists of two software tools: PR3D, a placement and routing tool for custom 3-D ICs based on standard cells, and 3-D Magic, a tool for designing, editing, and testing physical layout characteristics of 3-D ICs. The second contribution of this thesis is a performance analysis of the digital components of 3-D ICs. We use the above tools to determine the extent to which 3-D integration can improve timing, energy, and thermal performance. In doing so, we verify the estimates of stochastic computational models for 3-D IC interconnects and find that the models predict the optimal 3-D wire length to within 20% accuracy. We expand upon this analysis by examining how 3-D technology factors affect the optimal wire length that can be obtained. Our ultimate analysis extends this work by directly considering timing and energy in 3-D ICs. In all cases we find that significant performance improvements are possible. In contrast, thermal performance is expected to worsen with the use of 3-D integration. We examine precisely how thermal behavior scales in 3-D integration and determine quantitatively how the temperature may be controlled during the circuit placement process. We also show how advanced packaging(cont.) technologies may be leveraged to maintain acceptable die temperatures in 3-D ICs. Finally, we explore two issues for the future of 3-D integration. We determine how technology scaling impacts the effect of 3-D integration on circuit performance. We also consider how to improve the performance of digital components in a mixed-signal 3-D integrated circuit. We conclude with a look towards future 3-D IC design tools.by Shamik Das.Ph.D

Switched-Beam 60 GHz Endfire Circular Patch Planar Array With Integrated 2-D Butler Matrix for Chip-to-Chip Space-Surface Wave Communications

The complexity of chip interconnection on a multicore multichip (MCMC) module using the traditional wired interconnects increases with the chip count. The global wired interconnects that run across the entire module must be made longer as more chips are placed on a larger module. Since the interconnect delay grows as the square of the interconnect length, the global wired interconnects can become a major bottleneck of the computing performance in such systems. This dissertation presents a new type of hybrid space-surface wave interconnect (HSSW-I) using 60 GHz switched-beam antenna arrays to provide high-speed communication between the chips. The antennas communicate at near the speed of light through radiation in the air above the chips and through surface waves at the air-dielectric interface, and thus avoid lengthy delays. Each array consists of four center-fed circular patch elements with side vias in a 2 × 2 planar grid arrangement. The arrays enable multi-gigabits-per-second (Gbps) reconfigurable interchip communication when integrated with the proper chip transceivers. The main beam of the array is switched in the horizontal plane containing the chips, by changing the interelement phase shifts. The switching of the main beam is analyzed and verified through full-wave simulation. A compact two-dimensional (2-D) Butler matrix feed network is designed, implemented, and integrated with the circular patch planar array. The matrix is a four-input, four-output, i.e., 4 × 4 network consisting of four interconnected quadrature (90°) hybrid couplers and allows endfire scanning of the array main beam along the four diagonal directions in the horizontal plane. The realized antenna module is a thin multilayer microstrip (MS) structure with a footprint small enough to fit over a typical multicore chip. The antenna module provides a seamless and practical way to achieve reconfigurable interchip communication in MCMC systems. A multiantenna module (MAM) consisting of five antenna modules that emulates diagonal interchip communication in MCMC systems is fabricated. The simulation and measurement of the transmission coefficients between the antenna modules on the MAM are performed, and the signal-to-noise ratio (SNR) and signal-to-noise-plus-interference ratio (SNIR) of the links are calculated. A link decomposition simulation technique to determine the relative contribution of space and surface waves is also applied. A transmission link model is devised based on the leaky wave effect shown by the antenna arrays and the model coefficients are determined from the simulation data. The link model is then extrapolated at various distances and compared with more measurement and simulation results for verification. Finally, realistic link budget calculations are performed based on the measured and simulated data. The calculations show that the antenna modules using the HSSW-I can achieve raw data transfer rates up to 42.24 Gbps at 20 mm distance with low bit error rates (BERs) in the absence of interference, when used with the state-of-the-art 60 GHz complementary metal oxide semiconductor (CMOS) transceivers

An Intelligent Mobility Prediction Scheme for Location-Based Service over Cellular Communications Network

One of the trickiest challenges introduced by cellular communications networks is mobility prediction for Location Based-Services (LBSs). Hence, an accurate and efficient mobility prediction technique is particularly needed for these networks. The mobility prediction technique incurs overheads on the transmission process. These overheads affect properties of the cellular communications network such as delay, denial of services, manual filtering and bandwidth. The main goal of this research is to enhance a mobility prediction scheme in cellular communications networks through three phases. Firstly, current mobility prediction techniques will be investigated. Secondly, innovation and examination of new mobility prediction techniques will be based on three hypothesises that are suitable for cellular communications network and mobile user (MU) resources with low computation cost and high prediction success rate without using MU resources in the prediction process. Thirdly, a new mobility prediction scheme will be generated that is based on different levels of mobility prediction. In this thesis, a new mobility prediction scheme for LBSs is proposed. It could be considered as a combination of the cell and routing area (RA) prediction levels. For cell level prediction, most of the current location prediction research is focused on generalized location models, where the geographic extent is divided into regular-shape cells. These models are not suitable for certain LBSs where the objectives are to compute and present on-road services. Such techniques are the New Markov-Based Mobility Prediction (NMMP) and Prediction Location Model (PLM) that deal with inner cell structure and different levels of prediction, respectively. The NMMP and PLM techniques suffer from complex computation, accuracy rate regression and insufficient accuracy. In this thesis, Location Prediction based on a Sector Snapshot (LPSS) is introduced, which is based on a Novel Cell Splitting Algorithm (NCPA). This algorithm is implemented in a micro cell in parallel with the new prediction technique. The LPSS technique, compared with two classic prediction techniques and the experimental results, shows the effectiveness and robustness of the new splitting algorithm and prediction technique. In the cell side, the proposed approach reduces the complexity cost and prevents the cell level prediction technique from performing in time slots that are too close. For these reasons, the RA avoids cell-side problems. This research discusses a New Routing Area Displacement Prediction for Location-Based Services (NRADP) which is based on developed Ant Colony Optimization (ACO). The NRADP, compared with Mobility Prediction based on an Ant System (MPAS) and the experimental results, shows the effectiveness, higher prediction rate, reduced search stagnation ratio, and reduced computation cost of the new prediction technique

The ALICE Silicon Pixel Detector Control and Calibration Systems

The work presented in this thesis was carried out in the Silicon Pixel Detector (SPD) group of the ALICE experiment at the Large Hadron Collider (LHC). The SPD is the innermost part (two cylindrical layers of silicon pixel detec- tors) of the ALICE Inner Tracking System (ITS). During the last three years I have been strongly involved in the SPD hardware and software development, construction and commissioning. This thesis is focused on the design, development and commissioning of the SPD Control and Calibration Systems. I started this project from scratch. After a prototyping phase now a stable version of the control and calibration systems is operative. These systems allowed the detector sectors and half-barrels test, integration and commissioning as well as the SPD commissioning in the experiment. The integration of the systems with the ALICE Experiment Control System (ECS), DAQ and Trigger system has been accomplished and the SPD participated in the experimental December 2007 commissioning run. The complexity of the detectors, the high number of subcomponents and the harsh working environment make necessary the development of a control system parallel to the data acquisition. This online slow control, called Detector Control System (DCS), has the task of controlling and monitoring all hardware and software components of the detector and of the necessary infrastructures. The latter include the power distribution system, cool ing, interlock system, etc. In this scenario, the DCS assumes a key role. Its functionalities have extended well over the simple control and monitoring of the experiment. DCS, nowadays, are highly advanced and automated online data acquisition systems, with less stringent requirements compared to the DAQ. Moreover the SPD DCS has the unique feature of not only controlling but also operating the SPD front-end electronics. These requirements impose a high level of synchronization between the system components and a fast system response. The DCS, in this case, is a fundamental component for the detector calibration. The SPD DCS should be operated in the ALICE DCS framework hence a series of integration constraint should be applied to the system. Furthermore, in complex experiments such as ALICE, the detector operation is tightly bound to the connection and integration of the various systems such as DAQ, DCS, trigger system, Experiment Control System (ECS) and Offline framework. The operation of the SPD front-end electronics and services should be done at various levels of integration. At the first and bottom level it is required that each system runs safely and independently. At the second level the subsystem controls should be merged to form a unique entity. At this stage the components operation should be synchronized to reach the full detector operation. The third level requires the integration of the SPD control in the genera l ALICE DCS/ECS. These requirements have been fulfilled by designing the DCS with two main software layers. On the bottom a Supervisory Control And Data Acquisition (SCADA) layer controls and monitors the equipments. It is based on a commercial application, PVSS, and it also responsible of provide an user interface to the subsystem components. On top a Finite State Machine (FSM) Layer performs the logical connection between the SPD subsystems and it connects the SPD DCS with the ALICE DCS and ECS. PVSS is designed for slow control applications and it is not suitable for the direct control of the fast SPD front-end electronics. I designed a Front-End Device Server (FED Server) to interface the SCADA layer with the front-end electronics. The server receives macro-instructions from the SCADA and it operates autonomously the complex front-end electronics. The complexity of the detector calibration requires a high automation level and the integration of the calibration system with the ALICE calibration framework. In order to satisfy these requirements and provide the user with a simple and versatile interface, I decided to foresee two calibration scenarios. A calibration scenario, named DAQ ACTIVE, allows the fast detector calibration but it needs the control of the full detector and subsystems. A second calibration scenario, named DCS ONLY, slower than the DAQ ACTIVE scenario, allows the calibration of a detector partition without interference with the normal detector operation. The control and calibration systems have been used to characterize and test the SPD components before and after the integration in the detector, both in laboratory (DSF) and in the ALICE environment. Some calibration and control systems application examples as well as a brief overview of the detector performance evaluated during the commissioning phases are reported