Shortest Paths and Steiner Trees in VLSI Routing

Routing is one of the major steps in very-large-scale integration (VLSI) design. Its task is to find disjoint wire connections between sets of points on a chip, subject to numerous constraints. This problem is solved in a two-stage approach, which consists of so-called global and detailed routing steps. For each set of metal components to be connected, global routing reduces the search space by computing corridors in which detailed routing sequentially determines the desired connections as shortest paths. In this thesis, we present new theoretical results on Steiner trees and shortest paths, the two main mathematical concepts in routing. In the practical part, we give computational results of BonnRoute, a VLSI routing tool developed at the Research Institute for Discrete Mathematics at the University of Bonn. Interconnect signal delays are becoming increasingly important in modern chip designs. Therefore, the length of paths or direct delay measures should be taken into account when constructing rectilinear Steiner trees. We consider the problem of finding a rectilinear Steiner minimum tree (RSMT) that --- as a secondary objective --- minimizes a signal delay related objective. Given a source we derive some structural properties of RSMTs for which the weighted sum of path lengths from the source to the other terminals is minimized. Also, we present an exact algorithm for constructing RSMTs with weighted sum of path lengths as secondary objective, and a heuristic for various secondary objectives. Computational results for industrial designs are presented. We further consider the problem of finding a shortest rectilinear Steiner tree in the plane in the presence of rectilinear obstacles. The Steiner tree is allowed to run over obstacles; however, if it intersects an obstacle, then no connected component of the induced subtree must be longer than a given fixed length. This kind of length restriction is motivated by its application in VLSI routing where a large Steiner tree requires the insertion of repeaters which must not be placed on top of obstacles. We show that there are optimal length-restricted Steiner trees with a special structure. In particular, we prove that a certain graph (called augmented Hanan grid) always contains an optimal solution. Based on this structural result, we give an approximation scheme for the special case that all obstacles are of rectangular shape or are represented by at most a constant number of edges. Turning to the shortest paths problem, we present a new generic framework for Dijkstra's algorithm for finding shortest paths in digraphs with non-negative integral edge lengths. Instead of labeling individual vertices, we label subgraphs which partition the given graph. Much better running times can be achieved if the number of involved subgraphs is small compared to the order of the original graph and the shortest path problems restricted to these subgraphs is computationally easy. As an application we consider the VLSI routing problem, where we need to find millions of shortest paths in partial grid graphs with billions of vertices. Here, the algorithm can be applied twice, once in a coarse abstraction (where the labeled subgraphs are rectangles), and once in a detailed model (where the labeled subgraphs are intervals). Using the result of the first algorithm to speed up the second one via goal-oriented techniques leads to considerably reduced running time. We illustrate this with the routing program BonnRoute on leading-edge industrial chips. Finally, we present computational results of BonnRoute obtained on real-world VLSI chips. BonnRoute fulfills all requirements of modern VLSI routing and has been used by IBM and its customers over many years to produce more than one thousand different chips. To demonstrate the strength of BonnRoute as a state-of-the-art industrial routing tool, we show that it performs excellently on all traditional quality measures such as wire length and number of vias, but also on further criteria of equal importance in the every-day work of the designer

Heterogeneous Self-Reconfiguring Robotics

Self-reconfiguring (SR) robots are modular systems that can autonomously change shape, or reconfigure, for increased versatility and adaptability in unknown environments. In this thesis, we investigate planning and control for systems of non-identical modules, known as heterogeneous SR robots. Although previous approaches rely on module homogeneity as a critical property, we show that the planning complexity of fundamental algorithmic problems in the heterogeneous case is equivalent to that of systems with identical modules. Primarily, we study the problem of how to plan shape changes while considering the placement of specific modules within the structure. We characterize this key challenge in terms of the amount of free space available to the robot and develop a series of decentralized reconfiguration planning algorithms that assume progressively more severe free space constraints and support reconfiguration among obstacles. In addition, we compose our basic planning techniques in different ways to address problems in the related task domains of positioning modules according to function, locomotion among obstacles, self-repair, and recognizing the achievement of distributed goal-states. We also describe the design of a novel simulation environment, implementation results using this simulator, and experimental results in hardware using a planar SR system called the Crystal Robot. These results encourage development of heterogeneous systems. Our algorithms enhance the versatility and adaptability of SR robots by enabling them to use functionally specialized components to match capability, in addition to shape, to the task at hand

Approximation Algorithms for Network Design Problems

We consider different variants of network design problems. Given a set of points in the plane we search for a shortest interconnection of them. In this general formulation the problem is known as Steiner tree problem. We consider the special case of octilinear Steiner trees in the presence of hard and soft obstacles. In an octilinear Steiner tree the line segments connecting the points are allowed to run either in horizontal, vertical or diagonal direction. An obstacle is a connected region in the plane bounded by a simple polygon. No line segment of an octilinear Steiner tree is allowed to lie in the interior of a hard obstacle. If we intersect a Steiner tree with the interior of a soft obstacle, no connected component of the induced subtree is allowed to be longer than a given fixed length. We provide polynomial time approximation schemes for the octilinear Steiner tree problem in the presence of hard and soft obstacles. These were the first presented approximation schemes introduced for the problems. Additionally, we introduce a (2+epsilon)-approximation algorithm for soft obstacles. We then turn to Euclidean group Steiner trees. Instead of a set of fixed points we get for each point a set of potential locations (combined into groups) and we need to pick only one location of each group. The groups we consider lie inside disjoint regions fulfilling a special property so-called alpha-fatness. Roughly speaking, the term alpha-fat specifies the shape of the region in comparison to a disk. We give the first approximation algorithm for this problem and achieve an approximation ratio of (1+epsilon)(9.093alpha +1). Last, we consider Manhattan networks. They are allowed to contain edges only in horizontal and vertical direction. In contrast to Steiner trees they contain a shortest path between each pair of points. We introduce insights into the structure of Manhattan networks, particularly in the context of so-called staircases. We give three new approximation algorithms for the Manhattan network problem, the first with approximation ratio 3 and two algorithms with ratio 2. To this end we introduce two algorithms for the Manhattan network problem of staircases. The first algorithm solves the problem to optimality the second yields a 2-approximation. Variants of both algorithms are already known in the literature. Since we use a slightly different definition of staircases and we need special properties of them, we adopt the algorithms to our situation. The 2-approximation algorithms achieve the best known approximation ratio of an algorithm for the Manhattan network problem known so far. Last we give an idea how we could possibly find an algorithm with better approximation ratio

Timing-Constrained Global Routing with Buffered Steiner Trees

This dissertation deals with the combination of two key problems that arise in the physical design of computer chips: global routing and buffering. The task of buffering is the insertion of buffers and inverters into the chip's netlist to speed-up signal delays and to improve electrical properties of the chip. Insertion of buffers and inverters goes alongside with construction of Steiner trees that connect logical sources with possibly many logical sinks and have buffers and inverters as parts of these connections. Classical global routing focuses on packing Steiner trees within the limited routing space. Buffering and global routing have been solved separately in the past. In this thesis we overcome the limitations of the classical approaches by considering the buffering problem as a global, multi-objective problem. We study its theoretical aspects and propose algorithms which we implement in the tool BonnRouteBuffer for timing-constrained global routing with buffered Steiner trees. At its core, we propose a new theoretically founded framework to model timing constraints inherently within global routing. As most important sub-task we have to compute a buffered Steiner tree for a single net minimizing the sum of prices for delays, routing congestion, placement congestion, power consumption, and net length. For this sub-task we present a fully polynomial time approximation scheme to compute an almost-cheapest Steiner tree with a given routing topology and prove that an exact algorithm cannot exist unless P=NP. For topology computation we present a bicriteria approximation algorithm that bounds both the geometric length and the worst slack of the topology. To improve the practical results we present many heuristic modifications, speed-up- and post-optimization techniques for buffered Steiner trees. We conduct experiments on challenging real-world test cases provided by our cooperation partner IBM to demonstrate the quality of our tool. Our new algorithm could produce better solutions with respect to both timing and routability. After post-processing with gate sizing and Vt-assignment, we can even reduce the power consumption on most instances. Overall, our results show that our tool BonnRouteBuffer for timing-constrained global routing is superior to industrial state-of-the-art tools

Intra Region Routing

The custom integrated circuit routing problem normally requires partitioning into rectangular routing regions. Natural partitions usually result in regions that form both channels and areas . This dissertation introduces several new channel and area routing algorithms and measures their performance. A formal description of the channel routing problem is presented and a relationship is established between the selection of intervals for each track and the number of tracks in the completed channel. This relationship is used as an analysis tool that leads to the development of two new and highly effective channel routing algorithms: the Revised and LCP algorithms. The performance of these algorithms is compared against the Dogleg, Greedy, and several area routing algorithms over sets of randomly generated channels. The results indicate performance increases ranging from 2.74 to 34 times, depending on the characteristics of the channel. In area routing, a new Degree of Freedom (DOF) based algorithm is developed that is straightforward to implement, is extensible to multipoint nets and reports if a path does not exist to complete the net. The quality of area routing algorithms is measured by the difficulty of the areas that can be successfully routed over sets of randomly generated areas. An extended definition of Manhattan Area Measure (MAM) is introduced as a measure of the difficulty of completing the wiring for areas with multipoint nets. The results show that the DOF algorithm has higher completion rates than the Lee algorithm. This difference is greatest in areas with high aspect ratios. A new measure of the difficulty of an area is developed that places upper bounds on the performance of area routing algorithms. In areas with low aspect ratios, the drop in algorithm completion rates is closely related to this upper bound

Fast Repeater Tree Construction

Repeaters are used during physical design of chips to improve the electrical and timing properties of interconnections. They are added along Steiner trees that connect root gates to sinks, creating repeater trees. Their construction became a crucial part of chip design. We present a new algorithm to solve the repeater tree construction problem. We first present an extensive version of the Repeater Tree Problem. Our problem formulation encapsulates most of the constraints that have been studied so far. We also consider several aspects for the first time, for example, slew dependent required arrival times at repeater tree sinks. The employed technology, the properties of available repeaters and metal wires, the shape of the chip, the temperature, the voltages, and many other factors highly influence the results of repeater tree construction. To take all this into account, we extensively preprocess the environment to extract parameters for our algorithms. We first present an algorithm for Steiner tree creation and prove that our algorithm is able to create timing-efficient as well as cost-efficient trees. Our algorithm is based on a delay model that accurately describes the timing that one can achieve after repeater insertion upfront. Next, we deal with the problem of adding repeaters to a given Steiner tree. The predominantly used algorithms to solve this problem use dynamic programming. However, they have several drawbacks. Firstly, potential repeater positions along the Steiner tree have to be chosen upfront. Secondly, the algorithms strictly follow the given Steiner tree and miss optimization opportunities. Finally, dynamic programming causes high running times. We present our new buffer insertion algorithm, Fast Buffering, that overcomes these limitations. It is able to produce results with similar quality to a dynamic programming approach but a much better running time. In addition, we also present improvements to the dynamic programming approach that allows us to push the quality at the expense of a high running time. We have implemented our algorithms as part of the BonnTools physical design optimization suite developed at the Research Institute for Discrete Mathematics in cooperation with IBM. Our implementation deals with all tedious details of a grown real-world chip optimization environment. We have created extensive experimental results on challenging real-world test cases provided by our cooperation partner. Our algorithm can solve about 5.7 million instances per hour

A complete design path for the layout of flexible macros

XIV+172hlm.;24c

On the construction of rectilinear Steiner minimum trees among obstacles.

Rectilinear Steiner minimum tree (RSMT) problem asks for a shortest tree spanning a set of given terminals using only horizontal and vertical lines. Construction of RSMTs is an important problem in VLSI physical design. It is useful for both the detailed and global routing steps, and it is important for congestion, wire length and timing estimations during the floorplanning or placement step. The original RSMT problem assumes no obstacle in the routing region. However, in today’s designs, there can be many routing blockages, like macro cells, IP blocks and pre-routed nets. Therefore, the RSMT problem with blockages has become an important problem in practice and has received a lot of research attentions in the recent years. The RSMT problem has been shown to be NP-complete, and the introduction of obstacles has made this problem even more complicated.In the first part of this thesis, we propose an exact algorithm, called ObSteiner, for the construction of obstacle-avoiding RSMT (OARSMT) in the presence of complex rectilinear obstacles. Our work is developed based on the GeoSteiner approach in which full Steiner trees (FSTs) are first constructed and then combined into a RSMT. We modify and extend the algorithm to allow rectilinear obstacles in the routing region. We prove that by adding virtual terminals to each routing obstacle, the FSTs in the presence of obstacles will follow some very simple structures. A two-phase approach is then developed for the construction of OARSMTs. In the first phase, we generate a set of FSTs. In the second phase, the FSTs generated in the first phase are used to construct an OARSMT. Experimental results show that ObSteiner is able to handle problems with hundreds of terminals in the presence of up to two thousand obstacles, generating an optimal solution in a reasonable amount of time.In the second part of this thesis, we propose the OARSMT problem with slew constraints over obstacles. In modern VLSI designs, obstacles usually block a fraction of metal layers only making it possible to route over the obstacles. However, since buffers cannot be place on top of any obstacle, we should avoid routing long wires over obstacles. Therefore, we impose the slew constraints for the interconnects that are routed over obstacles. To deal with this problem, we analyze the optimal solutions and prove that the internal trees with signal direction over an obstacle will follow some simple structures. Based on this observation, we propose an exact algorithm, called ObSteiner with slew constraints, that is able to find an optimal solution in the extended Hanan grid. Experimental results show that the proposed algorithm is able to reduce nearly 5% routing resources on average in comparison with the OARSMT algorithm and is also very much faster.Huang, Tao.Thesis (Ph.D.)--Chinese University of Hong Kong, 2013.Includes bibliographical references (leaves [137]-144).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- The rectilinear Steiner minimum tree problem --- p.1Chapter 1.2 --- Applications --- p.3Chapter 1.3 --- Obstacle consideration --- p.5Chapter 1.4 --- Thesis outline --- p.6Chapter 1.5 --- Thesis contributions --- p.8Chapter 2 --- Background --- p.11Chapter 2.1 --- RSMT algorithms --- p.11Chapter 2.1.1 --- Heuristics --- p.11Chapter 2.1.2 --- Exact algorithms --- p.20Chapter 2.2 --- OARSMT algorithms --- p.30Chapter 2.2.1 --- Heuristics --- p.30Chapter 2.2.2 --- Exact algorithms --- p.33Chapter 3 --- ObSteiner - an exact OARSMT algorithm --- p.37Chapter 3.1 --- Introduction --- p.38Chapter 3.2 --- Preliminaries --- p.39Chapter 3.2.1 --- OARSMT problem formulation --- p.39Chapter 3.2.2 --- An exact RSMT algorithm --- p.40Chapter 3.3 --- OARSMT decomposition --- p.42Chapter 3.3.1 --- Full Steiner trees among complex obstacles --- p.42Chapter 3.3.2 --- More Theoretical results --- p.59Chapter 3.4 --- OARSMT construction --- p.62Chapter 3.4.1 --- FST generation --- p.62Chapter 3.4.2 --- Pruning of FSTs --- p.66Chapter 3.4.3 --- FST concatenation --- p.71Chapter 3.5 --- Incremental construction --- p.82Chapter 3.6 --- Experiments --- p.83Chapter 4 --- ObSteiner with slew constraints --- p.97Chapter 4.1 --- Introduction --- p.97Chapter 4.2 --- Problem Formulation --- p.100Chapter 4.3 --- Overview of our approach --- p.103Chapter 4.4 --- Internal tree structures in an optimal solution --- p.103Chapter 4.5 --- Algorithm --- p.126Chapter 4.5.1 --- EFST and SCIFST generation --- p.127Chapter 4.5.2 --- Concatenation --- p.129Chapter 4.5.3 --- Incremental construction --- p.131Chapter 4.6 --- Experiments --- p.131Chapter 5 --- Conclusion --- p.135Bibliography --- p.13

Techniques de routage pseudo-aléatoire pour une application micro-électronique

Résumé La problématique de routage est très actuelle. On en trouve des applications dans les GPS, les prévisions de trafic routier, mais aussi pour le prototypage sur FPGA, la fabrication de puces électroniques ou le trafic TCP/IP sur Internet. On trouve des publications sur le sujet depuis plusieurs dizaines d'années, mais on observe actuellement une recrudescence confirmant l'actualité, l'importance et la complexité de ce problème. Cette thèse concerne le routage et ses ressources pour une application dans un nouveau type de système micro-électronique, nommé le WaferBoardTM . Son noyau consiste en un circuit électronique intégré à l'échelle d'une tranche de silicium (wafer). Peu d'applications commerciales de la micro-électronique ont exploité ce niveau d'intégration. Ce système de prototypage rapide vise à réduire d'un ou deux ordres de grandeur le temps de développement de systèmes électroniques. Il nécessite un ensemble d'outils logiciel de support, dont un outil de routage très rapide, capable de produire des solutions valables en des temps de l'ordre de la minute, et de certaines fonctionnalités spécifiques, l'équilibrage de délai ou le reroutage à la volée, au sein d'une netlist déjà routée. La problématique de routage pour cette application peut être imagée comme suit. Étant donné un réseau routier régulier (les routes d’Amériques du Nord en version cartésienne par exemple) et 100,000 voitures au départ lundi à 8h a.m. dans tout le pays avec des sources et destinations très variées; calculer les chemins pour toutes les voitures de telle sorte qu'aucune ne prenne la même route dans la journée. Il est 7h59 a.m, vous avez 1 minute, et des ponts sont inaccessibles pour travaux, en voici la liste. Cet exemple simpliste donne une idée des ordres de grandeurs de la problématique de routage que l'on cherche à résoudre pour cette application. Un algorithme de routage prend en paramètres deux structures de données : un graphe (ou réseau d'interconnexions) constitué de n\oe{}uds (sommets) et d'arcsUn arc relie deux sommets du graphe, et une netlistDans ce contexte, un netlist réfère à une liste d'interconnexions entre composants, liste de n\oe{}uds électriques dont les points de départ et d'arrivée sont positionnés géographiquement. Ainsi, au lieu de voitures, il s'agit de router des signaux électriques dont les points de départ et d'arrivée sont dictés par la position des broches des composants placés sur le système de prototypage. Un réseau régulier maillé mufti-dimensionnel (plus généralement appelé « réseau d'interconnexions ») sert de réseau routier dont certaines routes sont défectueuses, des ponts inaccessibles. En effet, le réseau d'interconnexions est un circuit électronique intégré à l'échelle d'une tranche de silicium complète, ce qui implique la présence de défectuosités au sein de chaque circuit fabriqué. Contrairement aux circuits électroniques classiques, où chacun est testé et les défectueux écartés, une intégration à l'échelle de la tranche demande de fortes redondances au sein du circuit pour minimiser le taux de rejets. Pour l'application du WaferBoard, un certain nombre d'éléments du réseau d'interconnexions seront fort probablement défectueux sur chaque circuit produit; l'algorithme de routage se doit de prendre en compte ces éléments très particuliers. Cette contrainte ne se retrouve pas dans les applications plus classiques des routeurs que l'on retrouve dans les PCB, circuits FPGA ou circuits VLSI. D'autres contraintes s'appliquent à ce projet particulier : la latence induite par la technologie est environ un ordre de grandeur plus importante que celle dans les circuits sur PCB, ce qui impose un routage orienté vers sa réduction.----------Abstract The routing problem is very actual. Applications are found in GPS, road traffic forecast, but also for prototyping on FPGA, or TCP/IP traffic on the Internet. Publications on the subject have existed for several decades, but new publications keep appearing, confirming the importance and complexity of the problem. This thesis deals with routing and the resources it requires for a new category of micro-electronic applications, called the WaferBoard. It is an electronic circuit integrated at the wafer scale. Few commercial applications of micro-electronics have exploited this level of integration. This rapid prototyping system aims at reducing by one or two orders of magnitude the development time of digital circuits. It requires a very fast routing tool, capable of producing viable solutions in a few minutes, with dedicated functionality such as balancing delays and rerouting on the fly parts of a netlist. The routing problem for this application can be pictured as follows. Given a regular road network of the size of north america, if 100.000 cars were to start Monday 8 a.m. across the continent with a wide variety of sources and destinations; the challenge is to compute paths for all cars so none of them take the same route that day. It is 7:59 am, you have 1 minute, and some bridges are under road work: here is the list. This simplistic example gives an idea of the orders of magnitude of the problem that need to be solved for this application. A routing algorithm takes as input: a graph (or interconnection network) made of nodes and edges, and a netlst, a list of electrical nodes with starting and ending points physically placed. Therefore, instead of cars, the problem consists of routing electrical signals with points of departure and arrival dictated by the pin position of components placed on the prototyping system. A regular, multi-dimensional mesh (also called "interconnection network") serves as a road network, which contains defective roads and inaccessible bridges. Indeed, the interconnection network is an electronic circuit integrated across a full wafer, implying the presence of defects within each manufactured circuit. Unlike conventional electronic circuits, where each is tested and defective ones are set apart, wafer scale integrated applications require lots of redundancy in the circuit to minimize the rejection rate. In the WaferBoard, a number of elements of the interconnection network will be defective in each circuit; the routing algorithm must take into account these very specific elements. This constraint is not found in the classic applications of routers found in PCB, FPGA or VLSI circuits. Other restrictions apply to this particular project: the latency induced by the technology is about one order of magnitude greater than that in the circuits of PCBs, which requires a routing oriented towards computation time reduction. This constraint partly explains the network architecture used. Within the WaferIC, the shortest distance is not necessarily the one that offers the smallest latency. This property of the network complexifies the routing problem. Balancing delays within a group of arbitrary size nets is a necessary feature of the routing algorithm, and the difficulty is amplified by the computation time limit. Indeed, the interest of the application is to reduce the time for a user to test a circuit: the time of setup is extremely short, and estimated at a few minutes only