Optimization of polling systems with Bernoulli schedules

Optimization;Polling Systems;Queueing Theory;operations research

A survey on performance analysis of warehouse carousel systems

This paper gives an overview of recent research on the performance evaluation and design of carousel systems. We discuss picking strategies for problems involving one carousel, consider the throughput of the system for problems involving two carousels, give an overview of related problems in this area, and present an extensive literature review. Emphasis has been given on future research directions in this area

EUROPEAN CONFERENCE ON QUEUEING THEORY 2016

International audienceThis booklet contains the proceedings of the second European Conference in Queueing Theory (ECQT) that was held from the 18th to the 20th of July 2016 at the engineering school ENSEEIHT, Toulouse, France. ECQT is a biannual event where scientists and technicians in queueing theory and related areas get together to promote research, encourage interaction and exchange ideas. The spirit of the conference is to be a queueing event organized from within Europe, but open to participants from all over the world. The technical program of the 2016 edition consisted of 112 presentations organized in 29 sessions covering all trends in queueing theory, including the development of the theory, methodology advances, computational aspects and applications. Another exciting feature of ECQT2016 was the institution of the Takács Award for outstanding PhD thesis on "Queueing Theory and its Applications"

A Reactive and Cycle-True IP Emulator for MPSoC Exploration

The design of MultiProcessor Systems-on-Chip (MPSoC) emphasizes intellectual-property (IP)-based communication-centric approaches. Therefore, for the optimization of the MPSoC interconnect, the designer must develop traffic models that realistically capture the application behavior as executing on the IP core. In this paper, we introduce a Reactive IP Emulator (RIPE) that enables an effective emulation of the IP-core behavior in multiple environments, including bitand cycle-true simulation. The RIPE is built as a multithreaded abstract instruction-set processor, and it can generate reactive traffic patterns. We compare the RIPE models with cycle-true functional simulation of complex application behavior (tasksynchronization, multitasking, and input/output operations). Our results demonstrate high-accuracy and significant speedups. Furthermore, via a case study, we show the potential use of the RIPE in a design-space-exploration context

Discrete Time Analysis of Consolidated Transport Processes

Diese Arbeit beschäftigt sich mit der Entwicklung zeitdiskreter Modelle zur Analyse von Transportbündelungen. Mit den entwickelten Modellen für Bestands- und Fahrzeugbündelungen, insbesondere Milkrun-Systeme, kann eine detaillierte Leistungsbewertung in kurzer Zeit durchgeführt werden. Darüber hinaus erlauben die Modelle die Analyse der Umschlagslagerbündelungen, beispielweise Hub-und-Spoke-Netzwerke, indem sie im Rahmen einer Netzwerkanalyse mit einander verknüpft werden