A Hybrid Segmentation Pattern of Partial Transmission in Computer Networks to Reduce the Complexity Level

Partial transmission sequence (PTS) is seen as a related project in the framework of the Orthogonal Frequency Division ‎Multiplexing (OFDM) to suppress the medium to high Peak-to-Average Power Ratio problem. The PTS chart data is based on dividing the back into subdivisions and their weight by combining step-by-step factors. Despite the fact that PTS can reduce the high specifications. The Computational Complexity Level (CC) limits the scope of application to match PTS use with ground applications. In PTS, there are three main distribution schemes. Interleaving projects (IL-PTS), arbitrary and alternate (PR-PTS) and Ad-PTS. In this paper, another algorithm called the Hybrid Pseudo-Random and Interleaving Cosine Wave Shape ‎‎(H-PRC-PTS) is presented and the PR-PTS equilibrium is established by stabilizing the cousin waveform between languages (S-IL-C- PTS), which was suggested in the previous work. The results showed that the proposed algorithm could reduce the validity of PAPR as a PR-PTS scheme, although the CC level was significantly reduced

New methods of partial transmit sequence for reducing the high peak-to-average-power ratio with low complexity in the ofdm and f-ofdm systems

The orthogonal frequency division multiplexing system (OFDM) is one of the most important components for the multicarrier waveform design in the wireless communication standards. Consequently, the OFDM system has been adopted by many high-speed wireless standards. However, the high peak-to-average- power ratio (PAPR) is the main obstacle of the OFDM system in the real applications because of the non-linearity nature in the transmitter. Partial transmit sequence (PTS) is one of the effective PAPR reduction techniques that has been employed for reducing the PAPR value 3 dB; however, the high computational complexity is the main drawback of this technique. This thesis proposes novel methods and algorithms for reducing the high PAPR value with low computational complexity depending on the PTS technique. First, three novel subblocks partitioning schemes, Sine Shape partitioning scheme (SS-PTS), Subsets partitioning scheme (Sb-PTS), and Hybrid partitioning scheme (H-PTS) have been introduced for improving the PAPR reduction performance with low computational complexity in the frequency-domain of the PTS structure. Secondly, two novel algorithms, Grouping Complex iterations algorithm (G-C-PTS), and Gray Code Phase Factor algorithm (Gray-PF-PTS) have been developed to reduce the computational complexity for finding the optimum phase rotation factors in the time domain part of the PTS structure. Third, a new hybrid method that combines the Selective mapping and Cyclically Shifts Sequences (SLM-CSS-PTS) techniques in parallel has been proposed for improving the PAPR reduction performance and the computational complexity level. Based on the proposed methods, an improved PTS method that merges the best subblock partitioning scheme in the frequency domain and the best low-complexity algorithm in the time domain has been introduced to enhance the PAPR reduction performance better than the conventional PTS method with extremely low computational complexity level. The efficiency of the proposed methods is verified by comparing the predicted results with the existing modified PTS methods in the literature using Matlab software simulation and numerical calculation. The results that obtained using the proposed methods achieve a superior gain in the PAPR reduction performance compared with the conventional PTS technique. In addition, the number of complex addition and multiplication operations has been reduced compared with the conventional PTS method by about 54%, and 32% for the frequency domain schemes, 51% and 65% for the time domain algorithms, 18% and 42% for the combining method. Moreover, the improved PTS method which combines the best scheme in the frequency domain and the best algorithm in the time domain outperforms the conventional PTS method in terms of the PAPR reduction performance and the computational complexity level, where the number of complex addition and multiplication operation has been reduced by about 51% and 63%, respectively. Finally, the proposed methods and algorithms have been applied to the OFDM and Filtered-OFDM (F-OFDM) systems through Matlab software simulation, where F-OFDM refers to the waveform design candidate in the next generation technology (5G)

A new truncation algorithm of low hardware cost multiplier

Multiplier is one of the most inevitable arithmetic circuit in digital signal design. Multipliers dissipate high power and occupy significant amount of the die area. In this paper, a low-error architecture design of the pre-truncated parallel multiplier is presented. The coefficients word length has been truncated to reduce the multiplier size. This truncation scaled down the gate count and shortened the critical paths of partial product array. The statistical errors of the designed multiplier are calculated for different pre-truncate values and compared. The multiplier is implemented using Stratix III, FPGA device. The post fitting report is presented in this paper, which shows a saving of 36.9 % in resources usage, and a reduction of 17 % in propagation time delay

A digital polar transmitter for multi-band OFDM Ultra-WideBand

Linear power amplifiers used to implement the Ultra-Wideband standard must be backed off from optimum power efficiency to meet the standard specifications and the power efficiency suffers. The problem of low efficiency can be mitigated by polar modulation. Digital polar architectures have been employed on numerous wireless standards like GSM, EDGE, and WLAN, where the fractional bandwidths achieved are only about 1%, and the power levels achieved are often in the vicinity of 20 dBm. Can the architecture be employed on wireless standards with low-power and high fractional bandwidth requirements and yet achieve good power efficiency? To answer these question, this thesis studies the application of a digital polar transmitter architecture with parallel amplifier stages for UWB. The concept of the digital transmitter is motivated and inspired by three factors. First, unrelenting advances in the CMOS technology in deep-submicron process and the prevalence of low-cost Digital Signal processing have resulted in the realization of higher level of integration using digitally intensive approaches. Furthermore, the architecture is an evolution of polar modulation, which is known for high power efficiency in other wireless applications. Finally, the architecture is operated as a digital-to-analog converter which circumvents the use of converters in conventional transmitters. Modeling and simulation of the system architecture is performed on the Agilent Advanced Design System Ptolemy simulation platform. First, by studying the envelope signal, we found that envelope clipping results in a reduction in the peak-to-average power ratio which in turn improves the error vector magnitude performance (figure of merit for the study). In addition, we have demonstrated that a resolution of three bits suffices for the digital polar transmitter when envelope clipping is performed. Next, this thesis covers a theoretical derivation for the estimate of the error vector magnitude based on the resolution, quantization and phase noise errors. An analysis on the process variations - which result in gain and delay mismatches - for a digital transmitter architecture with four bits ensues. The above studies allow RF designers to estimate the number of bits required and the amount of distortion that can be tolerated in the system. Next, a study on the circuit implementation was conducted. A DPA that comprises 7 parallel RF amplifiers driven by a constant RF phase-modulated signal and 7 cascode transistors (individually connected in series with the bottom amplifiers) digitally controlled by a 3-bit digitized envelope signal to reconstruct the UWB signal at the output. Through the use of NFET models from the IBM 130-nm technology, our simulation reveals that our DPA is able to achieve an EVM of - 22 dB. The DPA simulations have been performed at 3.432 GHz centre frequency with a channel bandwidth of 528 MHz, which translates to a fractional bandwidth of 15.4%. Drain efficiencies of 13.2/19.5/21.0% have been obtained while delivering -1.9/2.5/5.5 dBm of output power and consuming 5/9/17 mW of power. In addition, we performed a yield analysis on the digital polar amplifier, based on unit-weighted and binary-weighted architecture, when gain variations are introduced in all the individual stages. The dynamic element matching method is also introduced for the unit-weighted digital polar transmitter. Monte Carlo simulations reveal that when the gain of the amplifiers are allowed to vary at a mean of 1 with a standard deviation of 0.2, the binary-weighted architecture obtained a yield of 79%, while the yields of the unit-weighted architectures are in the neighbourhood of 95%. Moreover, the dynamic element matching technique demonstrates an improvement in the yield by approximately 3%. Finally, a hardware implementation for this architecture based on software-defined arbitrary waveform generators is studied. In this section, we demonstrate that the error vector magnitude results obtained with a four-stage binary-weighted digital polar transmitter under ideal combining conditions fulfill the European Computer Manufacturers Association requirements. The proposed experimental setup, believed to be the first ever attempted, confirm the feasibility of a digital polar transmitter architecture for Ultra-Wideband. In addition, we propose a number of power combining techniques suitable for the hardware implementation. Spatial power combining, in particular, shows a high potential for the digital polar transmitter architecture. The above studies demonstrate the feasibility of the digital polar architecture with good power efficiency for a wideband wireless standard with low-power and high fractional bandwidth requirements