Speed Efficient Hardware Implementation Of Advanced Encryption Standard (Aes)

Cryptography plays a vital role in data security against the attacks from the third party. In this thesis, the focus is to leverage existing, commonly used cryptography algorithm which is the Advanced Encryption Standard (AES) and improve its speed performance. The motivation is to make encryption process as short as possible to aid in increasing a system's ability to process large amount of data. FPGA is chosen as the platform due to it does not have software overhead and is meant to be customized for real time applications. Most of the researches are done on the area of optimizing hardware resources to implement AES on FPGA. The methods of optimization include on the fly computations and looping architecture, where all these of methods reduce the speed. This thesis presents a high throughput design of the 128-bit AES algorithm using loop unrolling, pipelined architecture and LUT approach which is able to work in parallel to allow accurate synchronization in order to fulfill the real time application needs. The system design is coded using Verilog HDL in ModelSim and the hardware design is analyzed through Altera Cyclone II in Quartus II. The maximum throughput of 32 Gbits/s operating at 250 MHz for the encryption process can be achieved. Also, one full cycle of a 128-bit AES encryption only needs 41 clock cycles in order to get the encrypted data. The comparison with the related works is done and eventually achieved higher throughput than the related works by 3.47% and 22% respectively. The two objectives set in this thesis are achieved

Design and implementation of Area optimized 256 bit Advanced encryption standard on FPGA

This paper presents architecture of the Advanced Encryption Standard (AES-Rijndael) cryptosystem. The reconfigurable architecture is capable of handling all possible combinations of standard bit lengths (128,192,256) of data and key. The two main parts of AES algorithm, namely encryption and key expansion, are considered for optimization. The major optimization criteria considered are maximization of hardware reduction and path delay reduction. The fully rolled inner-pipelined architecture ensures lesser hardware complexity. A new AES algorithm with 256-bit keys (AES-256) was described in this paper, which is to be realized in Verilog Hardware Description Language on FPGA board. In this novel work, substantial improvement in performance in terms of area, power and dynamic speed will obtained. This will give low complexity architecture and will easily achieve low latency as well as high throughput. DOI: 10.17762/ijritcc2321-8169.15027

LEE: Light‐Weight Energy‐Efficient encryption algorithm for sensor networks

Data confidentiality in wireless sensor networks is mainly achieved by RC5 and Skipjack encryption algorithms. However, both algorithms have their weaknesses, for example RC5 supports variable-bit rotations, which are computationally expensive operations and Skipjack uses a key length of 80-bits, which is subject to brute force attack. In this paper we introduce a light-weight energy- fficient encryption-algorithm (LEE) for tiny embedded devices, such as sensor network nodes. We present experimental results of LEE under real sensor nodes operating in TinyOS. We also discuss the secrecy of our algorithm by presenting a security analysis of various tests and cryptanalytic attacks

Study of Data Security Algorithms using Verilog HDL

This paper describes an overview of data security algorithms and its performance evaluation. AES, RC5 and SHA algorithms have been taken under this study. Three different types of security algorithms used to analyze the performance study. The designs were implemented in Quartus-II software. The results obtained for encryption and decryption procedures show a significant improvement on the performance of the three algorithms. In this paper, 128-bit AES, 64-bit of RC5 and 512-bit of SHA256 encryption and Decryption has been made using Verilog Hardware Description Language and simulated using ModelSim

Improving Hardware Implementation of Cryptographic AES Algorithm and the Block Cipher Modes of Operation

With ever increasing Internet traffic, more business and financial transactions are being conducted online. This is even more so during these days of COVID-19 pandemic when traditional businesses such as traditional face to face educational systems have gone online requiring huge amount of data being exchanged over Internet. Increase in the volume of data sent over the Internet has also increased the security vulnerabilities such as challenging the confidentiality of data being sent over the Internet. Due to sheer volume, all data will need to be effectively encrypted. Due to increase in the volume of data, it is also important to have encryption/decryption functions to work at a higher speed to maintain the confidentiality of sensitive data. In this thesis, our goal is to enhance the hardware speed of encryption process of the standard AES scheme and its four variants such as AES-128, AES-192, AES-256 and new AES-512 and implement such functions on an FPGA. We also consider the FPGA implementation of different modes of AES operation. By employing parallelism and pipelining approach, we attempt to speed up various computational components of AES implementations using the Quartus II onto Intel’s FPGA. This approach shows improvement in the response speed, data throughput and latency