164 research outputs found
Design Approach to Implementation Of Arbitration Algorithm In Shared Bus Architectures (MPSoC)
The multiprocessor SoC designs have more than one processor and huge memory on the same chip. SoC consists of hardware cores and software cores ,multiple processors, embedded DRAM and connectors between cores .A wide range of MPSOC architectures have been developed over the past decade. This paper surveys the history of various On-Chip communication architectures present in the design of MPSoC. This acts as a primary factor of overall performance in complex SoC designs. Some of the various techniques that have driven the design of MpSoC has been discussed. Dynamically configurable communication architectures are found to improve the system performance. Currently On-chip interconnection networks are mostly implemented using shared buses which are the most common medium. The arbitration plays a crucial role in determining performance of bus-based system, as it assigns priorities, with which processor is granted the access to the shared communication resources. In the conventional arbitration algorithms there are some drawbacks such as bus starvation problem and low system performance. The bus should provide each component a flexible and utmost share of on-chip communication bandwidth and should improve the latency in access of the shared bus. The performance of SoC is improved using the probabilistic round robin algorithm with regard to the parameters, latency.Thus in this paper various issues related to bus arbitration related to design of MPSoC is analysed
Design And Simulation Of An Intelligent Adaptive Arbiter For Maximum Cpu Usage Of Multicore Processors
The recent technology in the world of microprocessor is blended with complex chips
that incorporate multiple processors dedicated for specific computational needs. Therefore, in
any shared memory system, an arbitration technique plays an important role to allocate access
to the shared resources. The major challenge dealt in the proposed research is the achievement
of maximum CPU utilization by exploiting its multiple cores with moderate bus bandwidth
allocation and low system latency. In order to tackle the aforesaid problems, an intelligent
adaptive arbitration technique has been proposed for the masters designed according to the
traffic behaviour of the data flow. The proposed intelligent adaptive arbitration technique is
implemented using STREAM, which is a synthetic benchmark program that measures
computational rate and sustainable memory bandwidth. In terms of performance analysis, the
proposed arbitration technique has been compared with the recent arbitration technique, such as
adaptive arbitration technique, dynamic lottery bus arbitration, round robin arbitration and static
fixed priority arbitration. To enhance the CPU utilization and bandwidth optimization, the
proposed arbitration technique has been modelled using SystemC and OpenMP threads using
the method of parallel programming to enable multi-core computing. Some recent arbitration
technique achieves fair bus bandwidth allocation up to some extent but fails to achieve
maximum CPU utilization, as the processor spends 95-96 % of their time idle and waits for
cache misses to be satisfied. The proposed arbitration technique is a strong case in favour of
maximum CPU usage and bandwidth optimization, as it consumes the processor cores up to
74% and also reduces the bandwidth fluctuation as well as latency
Multistage Packet-Switching Fabrics for Data Center Networks
Recent applications have imposed stringent requirements within the Data Center Network (DCN) switches in terms of scalability, throughput and latency. In this thesis, the architectural design of the packet-switches is tackled in different ways to enable the expansion in both the number of connected endpoints and traffic volume.
A cost-effective Clos-network switch with partially buffered units is proposed and two packet scheduling algorithms are described. The first algorithm adopts many simple and distributed arbiters, while the second approach relies on a central arbiter to guarantee an ordered packet delivery.
For an improved scalability, the Clos switch is build using a Network-on-Chip (NoC) fabric instead of the common crossbar units. The Clos-UDN architecture made with Input-Queued (IQ) Uni-Directional NoC modules (UDNs) simplifies the input line cards and obviates the need for the costly Virtual Output Queues (VOQs). It also avoids the need for complex, and synchronized scheduling processes, and offers speedup, load balancing, and good path diversity.
Under skewed traffic, a reliable micro load-balancing contributes to boosting the overall network performance. Taking advantage of the NoC paradigm, a wrapped-around multistage switch with fully interconnected Central Modules (CMs) is proposed. The architecture operates with a congestion-aware routing algorithm that proactively distributes the traffic load across the switching modules, and enhances the switch performance under critical packet arrivals.
The implementation of small on-chip buffers has been made perfectly feasible using the current technology. This motivated the implementation of a large switching architecture with an Output-Queued (OQ)
NoC fabric. The design merges assets of the output queuing, and
NoCs to provide high throughput, and smooth latency variations.
An approximate analytical model of the switch performance is also proposed.
To further exploit the potential of the NoC fabrics and their modularity features, a high capacity Clos switch with Multi-Directional NoC
(MDN) modules is presented. The Clos-MDN switching architecture exhibits a more compact layout than the Clos-UDN switch. It scales better and faster in port count and traffic load. Results achieved in this thesis demonstrate the high performance, expandability and programmability features of the proposed packet-switches which makes them promising candidates for the next-generation data center networking infrastructure
Comparison of multi-layer bus interconnection and a network on chip solution
Abstract. This thesis explains the basic subjects that are required to take in consideration when designing a network on chip solutions in the semiconductor world. For example, general topologies such as mesh, torus, octagon and fat tree are explained. In addition, discussion related to network interfaces, switches, arbitration, flow control, routing, error avoidance and error handling are provided. Furthermore, there is discussion related to design flow, a computer aided designing tools and a few comprehensive researches. However, several networks are designed for the minimum latency, although there are also versions which trade performance for decreased bus widths. These designed networks are compared with a corresponding multi-layer bus interconnection and both synthesis and register transfer level simulations are run. For example, results from throughput, latency, logic area and power consumptions are gathered and compared.
It was discovered that overall throughput was well balanced with the network on chip solutions, although its maximum throughput was limited by protocol conversions. For example, the multi-layer bus interconnection was capable of providing a few times smaller latencies and higher throughputs when only a single interface was injected at the time. However, with parallel traffic and high-performance requirements a network on chip solution provided better results, even though the difference decreased when performance requirements were lower. Furthermore, it was discovered that the network on chip solutions required approximately 3–4 times higher total cell area than the multi-layer bus interconnection and that resources were mainly located at network interfaces and switches. In addition, power consumption was approximately 2–3 times higher and was mostly caused by dynamic consumption.Monitasoisen väyläarkkitehtuurin ja tietokoneverkkomaisen ratkaisun vertailua. Tiivistelmä. Tutkielmassa käsitellään tärkeimpiä aihealueita, jotka tulee huomioida suunniteltaessa tietokoneverkkomaisia väyläratkaisuja puolijohdemaailmassa. Esimerkiksi yleiset rakenteet, kuten verkko-, torus-, kahdeksankulmio- ja puutopologiat käsitellään lyhyesti. Lisäksi alustetaan verkon liitäntäkohdat, kytkimet, vuorottelu, vuon hallinta, reititys, virheiden välttely ja -käsittely. Lopuksi kerrotaan suunnitteluvuon oleellisimmat välivaiheet ja niihin soveltuvia kaupallisia työkaluja, sekä käsitellään lyhyesti muutaman aiemman julkaisun tuloksia. Tutkielmassa käytetään suunnittelutyökalua muutaman tietokoneverkkomaisen ratkaisun toteutukseen ja tavoitteena on saavuttaa pienin mahdollinen latenssi. Toisaalta myös hieman suuremman latenssin versioita suunnitellaan, mutta pienemmillä väylänleveyksillä. Lisäksi suunniteltuja tietokoneverkkomaisia ratkaisuja vertaillaan perinteisempään monitasoiseen väyläarkkitehtuuriin. Esimerkiksi synteesi- ja simulaatiotuloksia, kuten logiikan vaatimaa pinta-alaa, tehonkulutusta, latenssia ja suorituskykyä, vertaillaan keskenään.
Tutkielmassa selvisi, että suunnittelutyökalulla toteutetut tietokoneverkkomaiset ratkaisut mahdollistivat tasaisemman suorituskyvyn, joskin niiden suurin saavutettu suorituskyky ja pienin latenssi määräytyivät protokollan käännöksen aiheuttamasta viiveestä. Tutkielmassa havaittiin, että perinteisemmillä menetelmillä saavutettiin noin kaksi kertaa suurempi suorituskyky ja pienempi latenssi, kun verkossa ei ollut muuta liikennettä. Rinnakkaisen liikenteen lisääntyessä tietokoneverkkomainen ratkaisu tarjosi keskimäärin paremman suorituskyvyn, kun sille asetetut tehokkuusvaateet olivat suuret, mutta suorituskykyvaatimuksien laskiessa erot kapenivat. Lisäksi huomattiin, että tietokoneverkkomaisten ratkaisujen käyttämä pinta-ala oli noin 3–4 kertaa suurempi kuin monitasoisella väyläarkkitehtuurilla ja että resurssit sijaitsivat enimmäkseen verkon liittymäkohdissa ja kytkimissä. Lisäksi tehonkulutuksen huomattiin olevan noin 2–3 kertaa suurempi, joskin sen havaittiin koostuvan pääosin dynaamisesta kulutuksesta
Driving the Network-on-Chip Revolution to Remove the Interconnect Bottleneck in Nanoscale Multi-Processor Systems-on-Chip
The sustained demand for faster, more powerful chips has been met by the
availability of chip manufacturing processes allowing for the integration of increasing
numbers of computation units onto a single die. The resulting outcome,
especially in the embedded domain, has often been called SYSTEM-ON-CHIP
(SoC) or MULTI-PROCESSOR SYSTEM-ON-CHIP (MP-SoC).
MPSoC design brings to the foreground a large number of challenges, one of
the most prominent of which is the design of the chip interconnection. With a
number of on-chip blocks presently ranging in the tens, and quickly approaching
the hundreds, the novel issue of how to best provide on-chip communication
resources is clearly felt.
NETWORKS-ON-CHIPS (NoCs) are the most comprehensive and scalable
answer to this design concern. By bringing large-scale networking concepts to
the on-chip domain, they guarantee a structured answer to present and future
communication requirements. The point-to-point connection and packet switching
paradigms they involve are also of great help in minimizing wiring overhead
and physical routing issues. However, as with any technology of recent inception,
NoC design is still an evolving discipline. Several main areas of interest
require deep investigation for NoCs to become viable solutions:
• The design of the NoC architecture needs to strike the best tradeoff among
performance, features and the tight area and power constraints of the onchip
domain.
• Simulation and verification infrastructure must be put in place to explore,
validate and optimize the NoC performance.
• NoCs offer a huge design space, thanks to their extreme customizability in
terms of topology and architectural parameters. Design tools are needed
to prune this space and pick the best solutions.
• Even more so given their global, distributed nature, it is essential to evaluate
the physical implementation of NoCs to evaluate their suitability for
next-generation designs and their area and power costs.
This dissertation performs a design space exploration of network-on-chip architectures,
in order to point-out the trade-offs associated with the design of
each individual network building blocks and with the design of network topology
overall. The design space exploration is preceded by a comparative analysis
of state-of-the-art interconnect fabrics with themselves and with early networkon-
chip prototypes. The ultimate objective is to point out the key advantages
that NoC realizations provide with respect to state-of-the-art communication
infrastructures and to point out the challenges that lie ahead in order to make
this new interconnect technology come true. Among these latter, technologyrelated
challenges are emerging that call for dedicated design techniques at all
levels of the design hierarchy. In particular, leakage power dissipation, containment
of process variations and of their effects. The achievement of the above
objectives was enabled by means of a NoC simulation environment for cycleaccurate
modelling and simulation and by means of a back-end facility for the
study of NoC physical implementation effects. Overall, all the results provided
by this work have been validated on actual silicon layout
Multistage Packet-Switching Fabrics for Data Center Networks
Recent applications have imposed stringent requirements within the Data Center Network (DCN) switches in terms of scalability, throughput and latency. In this thesis, the architectural design of the packet-switches is tackled in different ways to enable the expansion in both the number of connected endpoints and traffic volume.
A cost-effective Clos-network switch with partially buffered units is proposed and two packet scheduling algorithms are described. The first algorithm adopts many simple and distributed arbiters, while the second approach relies on a central arbiter to guarantee an ordered packet delivery.
For an improved scalability, the Clos switch is build using a Network-on-Chip (NoC) fabric instead of the common crossbar units. The Clos-UDN architecture made with Input-Queued (IQ) Uni-Directional NoC modules (UDNs) simplifies the input line cards and obviates the need for the costly Virtual Output Queues (VOQs). It also avoids the need for complex, and synchronized scheduling processes, and offers speedup, load balancing, and good path diversity.
Under skewed traffic, a reliable micro load-balancing contributes to boosting the overall network performance. Taking advantage of the NoC paradigm, a wrapped-around multistage switch with fully interconnected Central Modules (CMs) is proposed. The architecture operates with a congestion-aware routing algorithm that proactively distributes the traffic load across the switching modules, and enhances the switch performance under critical packet arrivals.
The implementation of small on-chip buffers has been made perfectly feasible using the current technology. This motivated the implementation of a large switching architecture with an Output-Queued (OQ)
NoC fabric. The design merges assets of the output queuing, and
NoCs to provide high throughput, and smooth latency variations.
An approximate analytical model of the switch performance is also proposed.
To further exploit the potential of the NoC fabrics and their modularity features, a high capacity Clos switch with Multi-Directional NoC
(MDN) modules is presented. The Clos-MDN switching architecture exhibits a more compact layout than the Clos-UDN switch. It scales better and faster in port count and traffic load. Results achieved in this thesis demonstrate the high performance, expandability and programmability features of the proposed packet-switches which makes them promising candidates for the next-generation data center networking infrastructure
Ethernet goes real-time: a survey on research and technological developments
Ethernet is the most popular LAN technology. Its low price and robustness, resulting from its
wide acceptance and deployment, has created an eagerness to expand its responsibilities to
the factory-floor, where real-time requirements are to be fulfilled. However, it is difficult to
build a real-time control network using Ethernet, because its MAC protocol, the 1-persistent
CSMA/CD protocol with the BEB collision resolution algorithm, has unpredictable delay
characteristics. Many anticipate that the recent technological advances in Ethernet such as
the emerging Fast/Gigabit Ethernet, micro-segmentation and full-duplex operation using
switches will also enable it to support time-critical applications. This technical report provides
a comprehensive look at the unpredictability inherent to Ethernet and at recent technological
advances towards real-time operation
A Scalable and Adaptive Network on Chip for Many-Core Architectures
In this work, a scalable network on chip (NoC) for future many-core architectures is proposed and investigated. It supports different QoS mechanisms to ensure predictable communication. Self-optimization is introduced to adapt the energy footprint and the performance of the network to the communication requirements. A fault tolerance concept allows to deal with permanent errors. Moreover, a template-based automated evaluation and design methodology and a synthesis flow for NoCs is introduced
Communication centric platforms for future high data intensive applications
The notion of platform based design is considered as a viable solution to boost the
design productivity by favouring reuse design methodology. With the scaling down of
device feature size and scaling up of design complexity, throughput limitations, signal
integrity and signal latency are becoming a bottleneck in future communication centric
System-on-Chip (SoC) design. This has given birth to communication centric platform
based designs.
Development of heterogeneous multi-core architectures has caused the on-chip
communication medium tailored for a specific application domain to deal with multidomain
traffic patterns. This makes the current application specific communication centric
platforms unsuitable for future SoC architectures.
The work presented in this thesis, endeavours to explore the current
communication media to establish the expectations from future on-chip interconnects. A
novel communication centric platform based design flow is proposed, which consists of
four communication centric platforms that are based on shared global bus, hierarchical
bus, crossbars and a novel hybrid communication medium. Developed with a smart
platform controller, the platforms support Open Core Protocol (OCP) socket standard,
allowing cores to integrate in a plug and play fashion without the need to reprogram the
pre-verified platforms. This drastically reduces the design time of SoC architectures. Each
communication centric platform has different throughput, area and power characteristics,
thus, depending on the design constraints, processing cores can be integrated to the most
appropriate communication platform to realise the desired SoC architecture.
A novel hybrid communication medium is also developed in this thesis, which
combines the advantages of two different types of communication media in a single SoC
architecture. The hybrid communication medium consists of crossbar matrix and shared
bus medium . Simulation results and implementation of WiMAX receiver as a real-life
example shows a 65% increase in data throughput than shared bus based communication
medium, 13% decrease in area and 11% decrease in power than crossbar based
communication medium.
In order to automate the generation of SoC architectures with optimised
communication architectures, a tool called SOCCAD (SoC Communication architecture
development) is developed. Components needed for the realisation of the given application
can be selected from the tool’s in-built library. Offering an optimised communication
centric placement, the tool generates the complete SystemC code for the system with
different interconnect architectures, along with its power and area characteristics. The
generated SystemC code can be used for quick simulation and coupled with efficient test
benches can be used for quick verification.
Network-on-Chip (NoC) is considered as a solution to the communication
bottleneck in future SoC architectures with data throughput requirements of over 10GB/s.
It aims to provide low power, efficient link utilisation, reduced data contention and
reduced area on silicon. Current on-chip networks, developed with fixed architectural
parameters, do not utilise the available resources efficiently. To increase this efficiency, a
novel dynamically reconfigurable NoC (drNoC) is developed in this thesis. The proposed
drNoC reconfigures itself in terms of switching, routing and packet size with the changing
communication requirements of the system at run time, thus utilising the maximum
available channel bandwidth. In order to increase the applicability of drNoC, the network
interface is designed to support OCP socket standard. This makes drNoC a highly reuseable
communication framework, qualifying it as a communication centric platform for
high data intensive SoC architectures. Simulation results show a 32% increase in data
throughput and 22-35% decrease in network delay when compared with a traditional NoC
with fixed parameters
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