The 1991 3rd NASA Symposium on VLSI Design

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2

Large space structures and systems in the space station era: A bibliography with indexes (supplement 03)

Bibliographies and abstracts are listed for 1221 reports, articles, and other documents introduced into the NASA scientific and technical information system between January 1, 1991 and June 30, 1991. Topics covered include large space structures and systems, space stations, extravehicular activity, thermal environments and control, tethering, spacecraft power supplies, structural concepts and control systems, electronics, advanced materials, propulsion, policies and international cooperation, vibration and dynamic controls, robotics and remote operations, data and communication systems, electric power generation, space commercialization, orbital transfer, and human factors engineering

Hardware Accelerator Design of a CCSDS Image Compression Standard Compliant Bit Plane Encoder

影像資料壓縮是航太任務與光學遙測系統的核心技術之一，根據太空任務需求，美國太空資料系統諮詢委員會(Consultative Committee for Space Data Systems，CCSDS)發展出新一代空間圖像壓縮標準規範，此演算法是由JPEG2000、SPIHT改良而來。其主要目標為將拍攝的衛星影像進行壓縮，並與地面接收站即時傳輸，致力於降低記憶體需求與維持良好的影像品質之間做最佳平衡。 在演算法方面，主要分成離散小波轉換(Discrete Wavelet Transform, DWT)與Bit-Plane Encoder(BPE)兩大部分。前者目的在於去除資料間的相關性(decorrelation)，而BPE則是將DWT所獲得的頻譜係數進行壓縮編碼，並提供資料率以及影像品質調整的機制。在DWT部分，文獻[1]已先將失真(lossy)模式的浮點數型態(floating type)與無失真(lossless)模式的整數型態(integer type)進行3 levels的離散小波轉換，硬體架構上則是採用9/7濾波器架構，並可支援不同的輸入影像寬度。 一般而言，BPE部分被視為整套壓縮系統在效能及硬體資源方面的瓶頸所在，本論文針對BPE部分，發展出一套有效的VLSI架構，以DWT的結果當作輸入，兩者之間的介面也經過係數的重組，以達到和前級的速率相同。利用管線化與平行度等技巧加速BPE內部的運算速度，BPE在儲存符號與字串的記憶體則是採用ping-pong buffer之技術。硬體設計的驗證是採用軟硬體交叉比對的方式，由於BPE在資料處理過程中具有關連性，因此要逐一分段驗證，確保前級模組功能正確後，再驗證後段的模組，最終目標則是與軟體壓縮影像後產生的位元流字串相同即可。功能驗證正確後的設計，最後在Xilinx Virtex-7 XC7VX330T FPGA上實現，其合成後的最大工作頻率可達到87.41MHZ。這相當於每秒可以處理10,000條以上，每條寬度8,192畫素的即時影像壓縮。Image compression is one the major techniques in various space missions and remote sensing systems. Consultative Committee for Space Data Systems (CCSDS) has developed a data compression standard for the tasks on the satellite. This algorithm is based on JPEG2000 and SPIHT. The purpose is compressing the satellite imagery and transmitting it to the ground earth station in real time while trying to reach the balance between memory buffer requirement and image quality. The CCSDS IDC algorithm consists of two major functional parts: Discrete Wavelet Transform(DWT) and Bit-Plane Encoder(BPE). DWT module aims at data decorrelation. After decorrelation, BPE module then encodes the coefficients decomposed by DWT and supports the options of data rate control and image quality adjustment. In thesis[1], both floating type and integer type DWTs have been implemented by using a 9/7 filter architecture. Both of them perform a 2-dimentional 3-level DWT decomposition with adaptive image width settings. The bit plane encoder is the key module of CCSDS IDC system. It is also regarded as the bottleneck of throughput performance and hardware resource consumption. This thesis presents an efficient VLSI architecture design of BPE hardware accelerator. It takes the result of DWT module as input, and employs an interface circuitry to cope with the throughput rate of the DWT module. The interface circuitry also reorganizes the received DWT coefficients from a word-level ordering to a bit-plane level ordering, which facilitates the processing of bit-plane based encoding. Parallel and pipelined processing techniques are adopted extensively in the BPE module design to achieve the target throughput rate. In addition, a ping-pong buffer strategy is employed to meet the throughput requirement of holding the generated symbols and bit-streams. The BPE design is verified by comparing the results generated by the software simulation model and the Verilog model. Due to the data dependence in BPE generated bit streams, the verification is conducted step by step to ensure the functional correctness of each module in the BPE design. The BPE module design is implemented in a Xilinx Virtex-7 XC7VX330T FPGA device with a maximum clock frequency of 87.41 MHz. This suggests a throughput rate of processing up to 10,000 8,192-pixel-wide lines per second.摘要 i Abstract ii 目錄 iv 圖目錄 vi 表目錄 viii 第一章 緒論 1 1.1 研究背景 1 1.2 研究動機及研究目標 2 1.3 文獻回顧 3 1.4 論文架構 5 第二章 影像資料壓縮原理 6 2.1基本原理介紹 6 2.1.1 離散小波轉換 7 2.1.2 熵編碼 8 2.2 CCSDS編碼演算法 10 2.2.1 以DWT為基礎的壓縮系統架構 10 2.2.2 區塊及階層式分解編碼 11 第三章 CCSDS 122.0-B-1影像壓縮標準之簡介 14 3.1 Bit-Plane Encoder演算法 14 3.1.1 Segment Header 15 3.1.2 Encode DC Coefficients 17 3.1.3 AC Coefficient Bit Depths Coding 21 3.1.4 Bit-plane Coding of AC Coefficients 21 第四章 位元平面編碼器電路設計 29 4.1系統方塊圖及模組IO 29 4.1.1硬體設計挑戰 29 4.1.2 BPE整體時序 30 4.1.3平行電路架構設計 32 4.2 記憶體配置規劃 41 4.2.1 DWT與BPE介面之記憶體規劃 41 4.2.2 符號及最佳編碼選項之記憶體規劃 43 4.2.3 字串記憶體規劃 43 4.3 硬體控制描述與模組之時序圖規劃 44 4.3.1 Depth Encoder 44 4.3.2 Quantize Predictor 45 4.3.3 DC Encoder 45 4.3.4 AC Stage 1~3 Scan Encoder 47 第五章 位元平面編碼器於FPGA之設計與實現 51 5.1 電路模擬與軟體驗證 51 5.1.1 電路波形圖觀察 51 5.1.2 軟硬體比對結果 57 5.2 RTL電路合成結果 60 第六章 結論及未來展望 64 參考文獻 6