49 research outputs found

    Imaging Sensors and Applications

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    In past decades, various sensor technologies have been used in all areas of our lives, thus improving our quality of life. In particular, imaging sensors have been widely applied in the development of various imaging approaches such as optical imaging, ultrasound imaging, X-ray imaging, and nuclear imaging, and contributed to achieve high sensitivity, miniaturization, and real-time imaging. These advanced image sensing technologies play an important role not only in the medical field but also in the industrial field. This Special Issue covers broad topics on imaging sensors and applications. The scope range of imaging sensors can be extended to novel imaging sensors and diverse imaging systems, including hardware and software advancements. Additionally, biomedical and nondestructive sensing applications are welcome

    Analog and Neuromorphic computing with a framework on a reconfigurable platform

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    The objective of the research is to demonstrate energy-efficient computing on a configurable platform, the Field Programmable Analog Array (FPAA), by leveraging analog strengths, along with a framework, to enable real-time systems on hardware. By taking inspiration from biology, fundamental blocks of neurons and synapses are built, understanding the computational advantages of such neural structures. To enable this computation and scale up from these modules, it is important to have an infrastructure that adapts by taking care of non-ideal effects like mismatches and variations, which commonly plague analog implementations. Programmability, through the presence of floating gates, helps to reduce these variations, thereby ultimately paving the path to take physical approaches to build larger systems in a holistic manner.Ph.D

    Modeling and Simulation in Engineering

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    The general aim of this book is to present selected chapters of the following types: chapters with more focus on modeling with some necessary simulation details and chapters with less focus on modeling but with more simulation details. This book contains eleven chapters divided into two sections: Modeling in Continuum Mechanics and Modeling in Electronics and Engineering. We hope our book entitled "Modeling and Simulation in Engineering - Selected Problems" will serve as a useful reference to students, scientists, and engineers

    Cutting Edge Nanotechnology

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    The main purpose of this book is to describe important issues in various types of devices ranging from conventional transistors (opening chapters of the book) to molecular electronic devices whose fabrication and operation is discussed in the last few chapters of the book. As such, this book can serve as a guide for identifications of important areas of research in micro, nano and molecular electronics. We deeply acknowledge valuable contributions that each of the authors made in writing these excellent chapters

    On the VCO/Frequency Divider Interface in Cryogenic CMOS PLL for Quantum Computing Applications

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    The availability of quantum microprocessors is mandatory, to efficiently run those quantum al-gorithms promising a radical leap forward in computation capability. Silicon-based nanostruc-tured qubits appear today as a very interesting approach, because of their higher information density, longer coherence times, fast operation gates, and compatibility with the actual CMOS technology. In particular, thanks to their phase noise properties, the actual CMOS RFIC Phase-Locked Loops (PLL) and Phase-Locked Oscillators (PLO) are interesting circuits to synthe-size control signals for spintronic qubits. In a quantum microprocessor, these circuits should op-erate close to the qubits, that is, at cryogenic temperatures. The lack of commercial cryogenic Design Kits (DK) may make the interface between the Voltage Controlled Oscillator (VCO) and the Frequency Divider (FD) a serious issue. Nevertheless, currently this issue has not been sys-tematically addressed in the literature. The aim of the present paper is to investigate the VCO/FD interface when the temperature drops from room to cryogenic. To this purpose, physi-cal models of electronics passive/active devices and equivalent circuits of VCO and the FD were developed at room and cryogenic temperatures. The modeling activity has led to design guide-lines for the VCO/FD interface, useful in the absence of cryogenic DKs

    Design of CMOS Digital Silicon Photomultipliers with ToF for Positron Emission Tomography

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    This thesis presents a contribution to the design of single-photon detectors for medical imaging. Specifically, the focus has been on the development of a pixel capable of single-photon counting in CMOS technology, and the associated sensor thereof. These sensors can work under low light conditions and provide timing information to determine the time-stamp of the incoming photons. For instance, this is particularly attractive for applications that rely either on time-of-flight measurements or on exponential decay determination of the light source, like positron emission tomography or fluorescence-lifetime imaging, respectively. This thesis proposes the study of the pixel architecture to optimize its performance in terms of sensitivity, linearity and signal to noise ratio. The design of the pixel has followed a bottom-up approach, taking care of the smallest building block and studying how the different architecture choices affect performance. Among the various building blocks needed, special emphasis has been placed on the following: • the Single-Photon Avalanche Diode (SPAD), a photodiode able to detect photons one by one; • the front-end circuitry of this diode, commonly called quenching and recharge circuit; • the Time-to-Digital Converter (TDC), which determines the timing performance of the pixel. The proposed architectural exploration provides a comprehensive insight into the design space of the pixel, allowing to determine the optimum design points in terms of sensor sensitivity, linearity or signal to noise ratio, thus helping designers to navigate through non-straightforward trade-offs. The proposed TDC is based on a voltage-controlled ring oscillator, since this architecture provides moderate time resolutions while keeping the footprint, the power, and conversion time relatively small. Two pseudo-differential delay stages have been studied, one with cross-coupled PMOS transistors and the other with cross-coupled inverters. Analytical studies and simulations have shown that cross-coupled inverters are the most appropriate to implement the TDC because they achieve better time resolution with smaller energy per conversion than cross-coupled PMOS transistor stages. A 1.3×1.3 mm2 pixel has been implemented in an 110 nm CMOS image sensor technology, to have the benefits of sub-micron technologies along with the cleanliness of CMOS image sensor technologies. The fabricated chips have been used to characterize the single-photon avalanche diodes. The results agree with expectations: a maximum photon detection probability of 46 % and a median dark count rate of 0.4 Hz/µm2 with an excess voltage of 3 V. Furthermore, the characterization of the TDC shows that the time resolution is below 100 ps, which agrees with post-layout simulations. The differential non-linearity is ±0.4LSB, and the integral non-linearity is ±6.1LSB. Photoemission occurs during characterization - an indication that the avalanches are not quenched properly. The cause of this has been identified to be in the design of the SPAD and the quenching circuit. SPADs are sensitive devices which maximum reverse current must be well defined and limited by the quenching circuit, otherwise unwanted effects like excessive cross-talk, noise, and power consumption may happen. Although this issue limits the operation of the implemented pixel, the information obtained during the characterization will help to avoid mistakes in future implementations

    Design of Discrete-time Chaos-Based Systems for Hardware Security Applications

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    Security of systems has become a major concern with the advent of technology. Researchers are proposing new security solutions every day in order to meet the area, power and performance specifications of the systems. The additional circuit required for security purposes can consume significant area and power. This work proposes a solution which utilizes discrete-time chaos-based logic gates to build a system which addresses multiple hardware security issues. The nonlinear dynamics of chaotic maps is leveraged to build a system that mitigates IC counterfeiting, IP piracy, overbuilding, disables hardware Trojan insertion and enables authentication of connecting devices (such as IoT and mobile). Chaos-based systems are also used to generate pseudo-random numbers for cryptographic applications.The chaotic map is the building block for the design of discrete-time chaos-based oscillator. The analog output of the oscillator is converted to digital value using a comparator in order to build logic gates. The logic gate is reconfigurable since different parameters in the circuit topology can be altered to implement multiple Boolean functions using the same system. The tuning parameters are control input, bifurcation parameter, iteration number and threshold voltage of the comparator. The proposed system is a hybrid between standard CMOS logic gates and reconfigurable chaos-based logic gates where original gates are replaced by chaos-based gates. The system works in two modes: logic locking and authentication. In logic locking mode, the goal is to ensure that the system achieves logic obfuscation in order to mitigate IC counterfeiting. The secret key for logic locking is made up of the tuning parameters of the chaotic oscillator. Each gate has 10-bit key which ensures that the key space is large which exponentially increases the computational complexity of any attack. In authentication mode, the aim of the system is to provide authentication of devices so that adversaries cannot connect to devices to learn confidential information. Chaos-based computing system is susceptible to process variation which can be leveraged to build a chaos-based PUF. The proposed system demonstrates near ideal PUF characteristics which means systems with large number of primary outputs can be used for authenticating devices

    High Voltage and Nanoscale CMOS Integrated Circuits for Particle Physics and Quantum Computing

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    HJIC

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    Compact Models for Integrated Circuit Design

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    This modern treatise on compact models for circuit computer-aided design (CAD) presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models. Featuring exercise problems at the end of each chapter and extensive references at the end of the book, the text supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices. It ensures even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts
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