2,167 research outputs found
A software definable MIMO testbed: architecture and functionality
Following the intensive theoretical studies of recently emerged MIMO technology, a variety of performance measures become important to investigate the challenges and trade-offs at various levels throughout MIMO system design process. This paper presents a review of the MIMO testbed recently set up at King’s College London. The architecture that distinguishes the testbed as a flexible and reconfigurable system is first preseneted. This includes both the hardware and software aspects, and is followed by a discussion of implementation methods and evaluation of system research capabilities
Efficient FPGA implementation of high-throughput mixed radix multipath delay commutator FFT processor for MIMO-OFDM
This article presents and evaluates pipelined architecture designs for an improved high-frequency Fast Fourier
Transform (FFT) processor implemented on Field Programmable Gate Arrays (FPGA) for Multiple Input Multiple Output
Orthogonal Frequency Division Multiplexing (MIMO-OFDM). The architecture presented is a Mixed-Radix Multipath Delay
Commutator. The presented parallel architecture utilizes fewer hardware resources compared to Radix-2 architecture,
while maintaining simple control and butterfly structures inherent to Radix-2 implementations. The high-frequency
design presented allows enhancing system throughput without requiring additional parallel data paths common in
other current approaches, the presented design can process two and four independent data streams in parallel
and is suitable for scaling to any power of two FFT size N. FPGA implementation of the architecture demonstrated
significant resource efficiency and high-throughput in comparison to relevant current approaches within
literature. The proposed architecture designs were realized with Xilinx System Generator (XSG) and evaluated
on both Virtex-5 and Virtex-7 FPGA devices. Post place and route results demonstrated maximum frequency
values over 400 MHz and 470 MHz for Virtex-5 and Virtex-7 FPGA devices respectively
Fast Power and Energy Efficiency Analysis of FPGA-based Wireless Base-band Processing
Nowadays, demands for high performance keep on increasing in the wireless
communication domain. This leads to a consistent rise of the complexity and
designing such systems has become a challenging task. In this context, energy
efficiency is considered as a key topic, especially for embedded systems in
which design space is often very constrained. In this paper, a fast and
accurate power estimation approach for FPGA-based hardware systems is applied
to a typical wireless communication system. It aims at providing power
estimates of complete systems prior to their implementations. This is made
possible by using a dedicated library of high-level models that are
representative of hardware IPs. Based on high-level simulations, design space
exploration is made a lot faster and easier. The definition of a scenario and
the monitoring of IP's time-activities facilitate the comparison of several
domain-specific systems. The proposed approach and its benefits are
demonstrated through a typical use case in the wireless communication domain.Comment: Presented at HIP3ES, 201
Large-Scale MIMO Detection for 3GPP LTE: Algorithms and FPGA Implementations
Large-scale (or massive) multiple-input multiple-output (MIMO) is expected to
be one of the key technologies in next-generation multi-user cellular systems,
based on the upcoming 3GPP LTE Release 12 standard, for example. In this work,
we propose - to the best of our knowledge - the first VLSI design enabling
high-throughput data detection in single-carrier frequency-division multiple
access (SC-FDMA)-based large-scale MIMO systems. We propose a new approximate
matrix inversion algorithm relying on a Neumann series expansion, which
substantially reduces the complexity of linear data detection. We analyze the
associated error, and we compare its performance and complexity to those of an
exact linear detector. We present corresponding VLSI architectures, which
perform exact and approximate soft-output detection for large-scale MIMO
systems with various antenna/user configurations. Reference implementation
results for a Xilinx Virtex-7 XC7VX980T FPGA show that our designs are able to
achieve more than 600 Mb/s for a 128 antenna, 8 user 3GPP LTE-based large-scale
MIMO system. We finally provide a performance/complexity trade-off comparison
using the presented FPGA designs, which reveals that the detector circuit of
choice is determined by the ratio between BS antennas and users, as well as the
desired error-rate performance.Comment: To appear in the IEEE Journal of Selected Topics in Signal Processin
Beamforming in MISO Systems: Empirical Results and EVM-based Analysis
We present an analytical, simulation, and experimental-based study of
beamforming Multiple Input Single Output (MISO) systems. We analyze the
performance of beamforming MISO systems taking into account implementation
complexity and effects of imperfect channel estimate, delayed feedback, real
Radio Frequency (RF) hardware, and imperfect timing synchronization. Our
results show that efficient implementation of codebook-based beamforming MISO
systems with good performance is feasible in the presence of channel and
implementation-induced imperfections. As part of our study we develop a
framework for Average Error Vector Magnitude Squared (AEVMS)-based analysis of
beamforming MISO systems which facilitates comparison of analytical,
simulation, and experimental results on the same scale. In addition, AEVMS
allows fair comparison of experimental results obtained from different wireless
testbeds. We derive novel expressions for the AEVMS of beamforming MISO systems
and show how the AEVMS relates to important system characteristics like the
diversity gain, coding gain, and error floor.Comment: Submitted to IEEE Transactions on Wireless Communications, November
200
Channel Sounding for the Masses: Low Complexity GNU 802.11b Channel Impulse Response Estimation
New techniques in cross-layer wireless networks are building demand for
ubiquitous channel sounding, that is, the capability to measure channel impulse
response (CIR) with any standard wireless network and node. Towards that goal,
we present a software-defined IEEE 802.11b receiver and CIR estimation system
with little additional computational complexity compared to 802.11b reception
alone. The system implementation, using the universal software radio peripheral
(USRP) and GNU Radio, is described and compared to previous work. By overcoming
computational limitations and performing direct-sequence spread-spectrum
(DS-SS) matched filtering on the USRP, we enable high-quality yet inexpensive
CIR estimation. We validate the channel sounder and present a drive test
campaign which measures hundreds of channels between WiFi access points and an
in-vehicle receiver in urban and suburban areas
Design and Implementation of a FPGA and DSP Based MIMO Radar Imaging System
The work presented in this paper is aimed at the implementation of a real-time multiple-input multiple-output (MIMO) imaging radar used for area surveillance. In this radar, the equivalent virtual array method and time-division technique are applied to make 16 virtual elements synthesized from the MIMO antenna array. The chirp signal generater is based on a combination of direct digital synthesizer (DDS) and phase locked loop (PLL). A signal conditioning circuit is used to deal with the coupling effect within the array. The signal processing platform is based on an efficient field programmable gates array (FPGA) and digital signal processor (DSP) pipeline where a robust beamforming imaging algorithm is running on. The radar system was evaluated through a real field experiment. Imaging capability and real-time performance shown in the results demonstrate the practical feasibility of the implementation
AirSync: Enabling Distributed Multiuser MIMO with Full Spatial Multiplexing
The enormous success of advanced wireless devices is pushing the demand for
higher wireless data rates. Denser spectrum reuse through the deployment of
more access points per square mile has the potential to successfully meet the
increasing demand for more bandwidth. In theory, the best approach to density
increase is via distributed multiuser MIMO, where several access points are
connected to a central server and operate as a large distributed multi-antenna
access point, ensuring that all transmitted signal power serves the purpose of
data transmission, rather than creating "interference." In practice, while
enterprise networks offer a natural setup in which distributed MIMO might be
possible, there are serious implementation difficulties, the primary one being
the need to eliminate phase and timing offsets between the jointly coordinated
access points.
In this paper we propose AirSync, a novel scheme which provides not only time
but also phase synchronization, thus enabling distributed MIMO with full
spatial multiplexing gains. AirSync locks the phase of all access points using
a common reference broadcasted over the air in conjunction with a Kalman filter
which closely tracks the phase drift. We have implemented AirSync as a digital
circuit in the FPGA of the WARP radio platform. Our experimental testbed,
comprised of two access points and two clients, shows that AirSync is able to
achieve phase synchronization within a few degrees, and allows the system to
nearly achieve the theoretical optimal multiplexing gain. We also discuss MAC
and higher layer aspects of a practical deployment. To the best of our
knowledge, AirSync offers the first ever realization of the full multiuser MIMO
gain, namely the ability to increase the number of wireless clients linearly
with the number of jointly coordinated access points, without reducing the per
client rate.Comment: Submitted to Transactions on Networkin
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