61 research outputs found
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Low power VCO-based analog-to-digital conversion
textThis dissertation presents novel two stage ADC architecture with a VCO based second stage. With the scaling of the supply voltages in modern CMOS process it is difficult to design high gain operational amplifiers needed for traditional voltage domain two-stage analog to digital converters. However time resolution continues to improve with the advancement in CMOS technology making VCO-based ADC more attractive. The nonlinearity in voltage-to-frequency transfer function is the biggest challenge in design of VCO based ADC. The hybrid approach used in this work uses a voltage domain first stage to determine the most significant bits and uses a VCO based second stage to quantize the small residue obtained from first stage. The architecture relaxes the gain requirement on the the first stage opamp and also relaxes the linearity requirements on the second stage VCO. The prototype ADC built in 65nm CMOS process achieves 63.7dB SNDR in 10MHz bandwidth while only consuming 1.1mW of power. The performance of the prototype chip is comparable to the state-of-art in terms of figure-of-merit but this new architecture uses significantly less circuit area.Electrical and Computer Engineerin
Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs
This Dissertation focusses on proving that background calibration using adaptive algorithms are low-cost, stable and effective methods for obtaining high accuracy in flash A/D converters. An integrated reference-less 3-bit flash ADC circuit has been successfully designed and taped out in UMC 180 nm CMOS technology in order to prove the efficiency of our proposed background calibration. References for ADC transitions have been virtually implemented built-in in the comparators dynamic-latch topology by a controlled mismatch added to each comparator input front-end. An external very simple DAC block (calibration bank) allows control the quantity of mismatch added in each comparator front-end and, therefore, compensate the offset of its effective transition with respect to the nominal value. In order to assist to the estimation of the offset of the prototype comparators, an auxiliary A/D converter with higher resolution and lower conversion speed than the flash ADC is used: a 6-bit capacitive-DAC SAR type. Special care in synchronization of analogue sampling instant in both ADCs has been taken into account.
In this thesis, a criterion to identify the optimum parameters of the flash ADC design with adaptive background calibration has been set. With this criterion, the best choice for dynamic latch architecture, calibration bank resolution and flash ADC resolution are selected.
The performance of the calibration algorithm have been tested, providing great programmability to the digital processor that implements the algorithm, allowing to choose the algorithm limits, accuracy and quantization errors in the arithmetic. Further, systematic controlled offset can be forced in the comparators of the flash ADC in order to have a more exhaustive test of calibration
A Low-Power, Reconfigurable, Pipelined ADC with Automatic Adaptation for Implantable Bioimpedance Applications
Biomedical monitoring systems that observe various physiological parameters or electrochemical reactions typically cannot expect signals with fixed amplitude or frequency as signal properties can vary greatly even among similar biosignals. Furthermore, advancements in biomedical research have resulted in more elaborate biosignal monitoring schemes which allow the continuous acquisition of important patient information. Conventional ADCs with a fixed resolution and sampling rate are not able to adapt to signals with a wide range of variation. As a result, reconfigurable analog-to-digital converters (ADC) have become increasingly more attractive for implantable biosensor systems. These converters are able to change their operable resolution, sampling rate, or both in order convert changing signals with increased power efficiency.
Traditionally, biomedical sensing applications were limited to low frequencies. Therefore, much of the research on ADCs for biomedical applications focused on minimizing power consumption with smaller bias currents resulting in low sampling rates. However, recently bioimpedance monitoring has become more popular because of its healthcare possibilities. Bioimpedance monitoring involves injecting an AC current into a biosample and measuring the corresponding voltage drop. The frequency of the injected current greatly affects the amplitude and phase of the voltage drop as biological tissue is comprised of resistive and capacitive elements. For this reason, a full spectrum of measurements from 100 Hz to 10-100 MHz is required to gain a full understanding of the impedance. For this type of implantable biomedical application, the typical low power, low sampling rate analog-to-digital converter is insufficient. A different optimization of power and performance must be achieved.
Since SAR ADC power consumption scales heavily with sampling rate, the converters that sample fast enough to be attractive for bioimpedance monitoring do not have a figure-of-merit that is comparable to the slower converters. Therefore, an auto-adapting, reconfigurable pipelined analog-to-digital converter is proposed. The converter can operate with either 8 or 10 bits of resolution and with a sampling rate of 0.1 or 20 MS/s. Additionally, the resolution and sampling rate are automatically determined by the converter itself based on the input signal. This way, power efficiency is increased for input signals of varying frequency and amplitude
Energy Efficient Techniques For Algorithmic Analog-To-Digital Converters
Analog-to-digital converters (ADCs) are key design blocks in
state-of-art image, capacitive, and biomedical sensing applications.
In these sensing applications, algorithmic ADCs are the preferred
choice due to their high resolution and low area advantages.
Algorithmic ADCs are based on the same operating principle as that
of pipelined ADCs. Unlike pipelined ADCs where the residue is
transferred to the next stage, an N-bit algorithmic ADC utilizes the
same hardware N-times for each bit of resolution. Due to the
cyclic nature of algorithmic ADCs, many of the low power techniques
applicable to pipelined ADCs cannot be
directly applied to algorithmic ADCs. Consequently, compared to those of
pipelined ADCs, the traditional implementations of algorithmic ADCs are
power inefficient.
This thesis presents two novel energy efficient techniques for algorithmic
ADCs. The first technique modifies the capacitors' arrangement of a
conventional flip-around configuration and amplifier sharing
technique, resulting in a low power and low area design solution. The
other technique is based on the unit
multiplying-digital-to-analog-converter approach. The proposed
approach exploits the power saving advantages of capacitor-shared technique
and capacitor-scaled technique. It is shown that, compared to
conventional techniques, the proposed techniques reduce the
power consumption of algorithmic ADCs by more than 85\%.
To verify the effectiveness of such approaches, two
prototype chips, a 10-bit 5 MS/s and a 12-bit 10 MS/s ADCs, are
implemented in a 130-nm CMOS process. Detailed design considerations
are discussed as well as the simulation and measurement results. According to the
simulation results, both designs achieve figures-of-merit of approximately 60 fJ/step,
making them some of the most power efficient ADCs to date
Energy Efficient Techniques For Algorithmic Analog-To-Digital Converters
Analog-to-digital converters (ADCs) are key design blocks in
state-of-art image, capacitive, and biomedical sensing applications.
In these sensing applications, algorithmic ADCs are the preferred
choice due to their high resolution and low area advantages.
Algorithmic ADCs are based on the same operating principle as that
of pipelined ADCs. Unlike pipelined ADCs where the residue is
transferred to the next stage, an N-bit algorithmic ADC utilizes the
same hardware N-times for each bit of resolution. Due to the
cyclic nature of algorithmic ADCs, many of the low power techniques
applicable to pipelined ADCs cannot be
directly applied to algorithmic ADCs. Consequently, compared to those of
pipelined ADCs, the traditional implementations of algorithmic ADCs are
power inefficient.
This thesis presents two novel energy efficient techniques for algorithmic
ADCs. The first technique modifies the capacitors' arrangement of a
conventional flip-around configuration and amplifier sharing
technique, resulting in a low power and low area design solution. The
other technique is based on the unit
multiplying-digital-to-analog-converter approach. The proposed
approach exploits the power saving advantages of capacitor-shared technique
and capacitor-scaled technique. It is shown that, compared to
conventional techniques, the proposed techniques reduce the
power consumption of algorithmic ADCs by more than 85\%.
To verify the effectiveness of such approaches, two
prototype chips, a 10-bit 5 MS/s and a 12-bit 10 MS/s ADCs, are
implemented in a 130-nm CMOS process. Detailed design considerations
are discussed as well as the simulation and measurement results. According to the
simulation results, both designs achieve figures-of-merit of approximately 60 fJ/step,
making them some of the most power efficient ADCs to date
A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for Monolithic Active Pixel Sensors
International audienceA 4 bit very low power and low incoming signal analog to digital converter (ADC) using a double sampling switched capacitor technique, designed for use in CMOS monolithic active pixels sensor readout, has been implemented in 0.35μm CMOS technology. A non-resetting sample and hold stage is integrated to amplify the incoming signal by 4. This first stage compensates both the amplifier offset effect and the input common mode voltage fluctuations. The converter is composed of a 2.5 bit pipeline stage followed by a 2 bit flash stage. This prototype consists of 4 ADC double-channels; each one is sampling at 50MS/s and dissipates only 2.6mW at 3.3V supply voltage. A bias pulsing stage is integrated in the circuit. Therefore, the analog part is switched OFF or ON in less than 1μs. The size for the layout is 80μm*0.9mm. This corresponds to the pitch of 4 pixel columns, each one is 20μm wide
A very low power and low signal 5 bit 50 M samples/s double sampling pipelined ADC for Monolithic Active Pixel Sensors in high energy physics and biomedical imaging applications
International audienc
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Design Techniques for High-Performance SAR A/D Converters
The design of electronics needs to account for the non-ideal characteristics of the device technologies used to realize practical circuits. This is particularly important in mixed analog-digital design since the best device technologies are very different for digital compared to analog circuits. One solution for this problem is to use a calibration correction approach to remove the errors introduced by devices, but this adds complexity and power dissipation, as well as reducing operation speed, and so must be optimised. This thesis addresses such an approach to improve the performance of certain types of analog-to-digital converter (ADC) used in advanced telecommunications, where speed, accuracy and power dissipation currently limit applications. The thesis specifically focuses on the design of compensation circuits for use in successive approximation register (SAR) ADCs.
ADCs are crucial building blocks in communication systems, in general, and for mobile networks, in particular. The recently launched fifth generation of mobile networks (5G) has required new ADC circuit techniques to meet the higher speed and lower power dissipation requirements for 5G technology. The SAR has become one of the most favoured architectures for designing high-performance ADCs, but the successive nature of the circuit operation makes it difficult to reach ∼GS/s sampling rates at reasonable power consumption.
Here, two calibration techniques for high-performance SAR ADCs are presented. The first uses an on-chip stochastic-based mismatch calibration technique that is able to accurately compute and compensate for the mismatch of a capacitive DAC in a SAR ADC. The stochastic nature of the proposed calibration method enables determination of the mismatch of the CAPDAC with a resolution much better than that of the DAC. This allows the unit capacitor to scale down to as low as 280aF for a 9-bit DAC. Since the CAP-DAC causes a large part of the overall dynamic power consumption and directly determines both the sizes of the driving and sampling switches and the size of the input capacitive load of the ADC and the kT/C noise power, a small CAP-DAC helps the power efficiency. To validate the proposed calibration idea, a 10-bit asynchronous SAR ADC was fabricated in 28-nm CMOS. Measurement results show that the proposed stochastic calibration improves the ADC’s SFDR and SNDR by 14.9 dB, 11.5 dB, respectively. After calibration, the fabricated SAR ADC achieves an ENOB of 9.14 bit at a sampling rate of 85 MS/s, resulting in a Walden FoM of 10.9 fJ/c-s.
The second calibration technique is a timing-skew calibration for a time-interleaved (TI) SAR ADC that calibrates/computes the inter-channel timing and offset mismatch simultaneously. Simulation results show the effectiveness of this calibration method. When used together, the proposed mismatch calibration technique and the timing-skew
calibration technique enables a TI SAR ADC to be designed that can achieve a sampling rate of ∼GS/s with 10-bit resolution and a power consumption as low as ∼10mW; specifications that satisfy the requirements of 5G technology
Caratterizzazione dello spazio architetturale di un amplificatore transconduttivo
Il presente lavoro di tesi affronta il problema della progettazione analogica a livello di sistema studiando un convertitore analogico/digitale di tipo pipeline ad elevate prestazioni in tecnologia CMOS a 0.13 um. Più specificamente, viene studiato l’amplificatore interstadio al fine di valutare l’ottimalità delle specifiche richieste nel progetto originale. Viene applicata una metodologia di progetto basata sulla esplorazione e caratterizzazione dello spazio architetturale di interesse, volta alla creazione di una libreria (Piattaforma Analogica) che racchiuda sia modelli di prestazioni dell’ amplificatore sia modelli comportamentali dello stesso da utilizzarsi per progettazione ad alto livello. Inizialmente, viene effettuata un’ analisi del primo stadio del convertitore pipeline volta a ricavare le specifiche del blocco amplificatore. La metodologia prevede un campionamento dello spazio delle prestazioni attraverso simulazione di configurazioni generate perturbando il progetto originale. Al fine di specificare lo spazio di campionamento, vengono ricavate delle relazioni che vincolano le dimensioni dei singoli dispositivi imponendo condizioni di polarizzazione, minimo guadagno e minima banda. Le relazioni vengono quindi manipolate al fine di ottenere uno schema valutativo, basato su MATLAB/Ocean, in grado di generare configurazioni casuali del circuito che rispettano le relazioni stesse. Un insieme di indici di prestazione viene ricavato dai dati delle simulazioni cui si ricorre dato lo scarso potere predittivo dei modelli analitici. Infatti, con le moderne tecnologie CMOS i parametri di merito sono legati alle dimensioni dei dispositivi attraverso equazioni non esprimibili in forma analitica. Gli indici di prestazione vengono utilizzati per la creazione di un modello di prestazione il cui scopo è di vincolare i parametri del modello comportamentale corrispondente a valori effettivamente ottenibili dall’architettura prescelta. Tale modello di prestazione può essere utilizzato per selezionare, tramite ottimizzazione a livello di sistema, un insieme di specifiche ottime per l’amplificatore in esame
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