Swarm-Based Spatial Sorting

Purpose: To present an algorithm for spatially sorting objects into an annular structure. Design/Methodology/Approach: A swarm-based model that requires only stochastic agent behaviour coupled with a pheromone-inspired "attraction-repulsion" mechanism. Findings: The algorithm consistently generates high-quality annular structures, and is particularly powerful in situations where the initial configuration of objects is similar to those observed in nature. Research limitations/implications: Experimental evidence supports previous theoretical arguments about the nature and mechanism of spatial sorting by insects. Practical implications: The algorithm may find applications in distributed robotics. Originality/value: The model offers a powerful minimal algorithmic framework, and also sheds further light on the nature of attraction-repulsion algorithms and underlying natural processes.Comment: Accepted by the Int. J. Intelligent Computing and Cybernetic

Deployment Strategies of Multiple Aerial BSs for User Coverage and Power Efficiency Maximization

Unmanned aerial vehicle (UAV) based aerial base stations (BSs) can provide rapid communication services to ground users and are thus promising for future communication systems. In this paper, we consider a scenario where no functional terrestrial BSs are available and the aim is deploying multiple aerial BSs to cover a maximum number of users within a certain target area. To this end, we first propose a naive successive deployment method, which converts the non-convex constraints in the involved optimization into a combination of linear constraints through geometrical relaxation. Then we investigate a deployment method based on K-means clustering. The method divides the target area into K convex subareas, where within each subarea, a mixed integer non-linear problem (MINLP) is solved. An iterative power efficient technique is further proposed to improve coverage probability with reduced power. Finally, we propose a robust technique for compensating the loss of coverage probability in the existence of inaccurate user location information (ULI). Our simulation results show that, the proposed techniques achieve an up to 30% higher coverage probability when users are not distributed uniformly. In addition, the proposed simultaneous deployment techniques, especially the one using iterative algorithm improve power-efficiency by up to 15% compared to the benchmark circle packing theory

Automatic synthesis of analog layout : a survey

A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon

Mapping constrained optimization problems to quantum annealing with application to fault diagnosis

Current quantum annealing (QA) hardware suffers from practical limitations such as finite temperature, sparse connectivity, small qubit numbers, and control error. We propose new algorithms for mapping boolean constraint satisfaction problems (CSPs) onto QA hardware mitigating these limitations. In particular we develop a new embedding algorithm for mapping a CSP onto a hardware Ising model with a fixed sparse set of interactions, and propose two new decomposition algorithms for solving problems too large to map directly into hardware. The mapping technique is locally-structured, as hardware compatible Ising models are generated for each problem constraint, and variables appearing in different constraints are chained together using ferromagnetic couplings. In contrast, global embedding techniques generate a hardware independent Ising model for all the constraints, and then use a minor-embedding algorithm to generate a hardware compatible Ising model. We give an example of a class of CSPs for which the scaling performance of D-Wave's QA hardware using the local mapping technique is significantly better than global embedding. We validate the approach by applying D-Wave's hardware to circuit-based fault-diagnosis. For circuits that embed directly, we find that the hardware is typically able to find all solutions from a min-fault diagnosis set of size N using 1000N samples, using an annealing rate that is 25 times faster than a leading SAT-based sampling method. Further, we apply decomposition algorithms to find min-cardinality faults for circuits that are up to 5 times larger than can be solved directly on current hardware.Comment: 22 pages, 4 figure