Integrated chaos generators

This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.Comisión Interministerial de Ciencia y Tecnología 1FD97-1611(TIC)European Commission ESPRIT 3110

Cascading CMOS-Based Chaotic Maps for Improved Performance and Its Application in Efficient RNG Design

We present a general framework for improving the chaotic properties of CMOS-based chaotic maps by cascading multiple maps in series. Along with two novel chaotic map topologies, we present the 45 $nm$ designs for four CMOS-based discrete-time chaotic map topologies. With the help of the bifurcation plot and three established entropy measures, namely, Lyapunov exponent, Kolmogorov entropy, and correlation coefficient, we present an extensive chaotic performance analysis on eight unique map circuits (two under each topology) to show that under certain constraints, the cascading scheme can significantly elevate the chaotic performance. The improved chaotic entropy benefits many security applications and is demonstrated using a novel random number generator (RNG) design. Unlike conventional mathematical chaotic map-based digital pseudo-random number generators (PRNG), this proposed design is not completely deterministic due to the high susceptibility of the core analog circuit to inevitable noise that renders this design closer to a true random number generator (TRNG). By leveraging the improved chaotic performance of the transistor-level cascaded maps, significantly low area and power overhead are achieved in the RNG design. The cryptographic applicability of the RNG is verified as the generated random sequences pass four standard statistical tests namely, NIST, FIPS, Diehard, and TestU01

Ultra-high-frequency piecewise-linear chaos using delayed feedback loops

We report on an ultra-high-frequency (> 1 GHz), piecewise-linear chaotic system designed from low-cost, commercially available electronic components. The system is composed of two electronic time-delayed feedback loops: A primary analog loop with a variable gain that produces multi-mode oscillations centered around 2 GHz and a secondary loop that switches the variable gain between two different values by means of a digital-like signal. We demonstrate experimentally and numerically that such an approach allows for the simultaneous generation of analog and digital chaos, where the digital chaos can be used to partition the system's attractor, forming the foundation for a symbolic dynamics with potential applications in noise-resilient communications and radar

A 2D Chaotic Oscillator for Analog IC

In this paper, we have proposed the design of an analog two-dimensional (2D) discrete-time chaotic oscillator. 2D chaotic systems are studied because of their more complex chaotic behavior compared to one-dimensional (1D) chaotic systems. The already published works on 2D chaotic systems are mainly focused either on the complex analytical combinations of familiar 1D chaotic maps such as Sine map, Logistic map, Tent map, and so on, or off-the-shelf component-based analog circuits. Due to complex hardware requirements, neither of them is feasible for hardware-efficient integrated circuit (IC) implementations. To the best of our knowledge, this proposed work is the first-ever report of an analog 2D discrete-time chaotic oscillator design that is suitable for hardware-constrained IC implementations. The chaotic performance of the proposed design is analyzed with bifurcation plots, the transient response, 2D Lyapunov exponent, and correlation coefficient measurements. It is demonstrated that the proposed design exhibits promising chaotic behavior with low hardware cost. The real-world application of the proposed 2D chaotic oscillator is presented in a random number generator (RNG) design. The applicability of the RNG in cryptography is verified by passing the generated random sequence through four standard statistical tests namely, NIST, FIPS, TestU01, and Diehard

Design of Discrete-time Chaos-Based Systems for Hardware Security Applications

Security of systems has become a major concern with the advent of technology. Researchers are proposing new security solutions every day in order to meet the area, power and performance specifications of the systems. The additional circuit required for security purposes can consume significant area and power. This work proposes a solution which utilizes discrete-time chaos-based logic gates to build a system which addresses multiple hardware security issues. The nonlinear dynamics of chaotic maps is leveraged to build a system that mitigates IC counterfeiting, IP piracy, overbuilding, disables hardware Trojan insertion and enables authentication of connecting devices (such as IoT and mobile). Chaos-based systems are also used to generate pseudo-random numbers for cryptographic applications.The chaotic map is the building block for the design of discrete-time chaos-based oscillator. The analog output of the oscillator is converted to digital value using a comparator in order to build logic gates. The logic gate is reconfigurable since different parameters in the circuit topology can be altered to implement multiple Boolean functions using the same system. The tuning parameters are control input, bifurcation parameter, iteration number and threshold voltage of the comparator. The proposed system is a hybrid between standard CMOS logic gates and reconfigurable chaos-based logic gates where original gates are replaced by chaos-based gates. The system works in two modes: logic locking and authentication. In logic locking mode, the goal is to ensure that the system achieves logic obfuscation in order to mitigate IC counterfeiting. The secret key for logic locking is made up of the tuning parameters of the chaotic oscillator. Each gate has 10-bit key which ensures that the key space is large which exponentially increases the computational complexity of any attack. In authentication mode, the aim of the system is to provide authentication of devices so that adversaries cannot connect to devices to learn confidential information. Chaos-based computing system is susceptible to process variation which can be leveraged to build a chaos-based PUF. The proposed system demonstrates near ideal PUF characteristics which means systems with large number of primary outputs can be used for authenticating devices

Chaos-based high-EMC spread-spectrum clock generator

4noThis paper proposes a spread-spectrum clock generator which is meant to respect EMC norm compliance from standard regulations. This is obtained through a frequency modulation driven by a chaotic signal, i.e. through the injection of a chaos-based jitter, so to avoid strict periodicity in the clock and thus high peaks in its power spectral density. The circuit has been designed in 0.35μm technology; measurements from prototypes show EMC improvement of approximately 18dB with respect to the reference case.partially_openopenDe Michele L. A.; Pareschi F.; Rovatti R.; Setti G.De Michele, L. A.; Pareschi, F.; Rovatti, R.; Setti, G

Communication Subsystems for Emerging Wireless Technologies

The paper describes a multi-disciplinary design of modern communication systems. The design starts with the analysis of a system in order to define requirements on its individual components. The design exploits proper models of communication channels to adapt the systems to expected transmission conditions. Input filtering of signals both in the frequency domain and in the spatial domain is ensured by a properly designed antenna. Further signal processing (amplification and further filtering) is done by electronics circuits. Finally, signal processing techniques are applied to yield information about current properties of frequency spectrum and to distribute the transmission over free subcarrier channels

Pseudo-Random Bit Generator Using Chaotic Seed for Cryptographic Algorithm in Data Protection of Electric Power Consumption

Cryptographic algorithms have played an important role in information security for protecting privacy. The literature provides evidence that many types of chaotic cryptosystems have been proposed. These chaotic systems encode information to obviate its orbital instability and ergodicity. In this work, a pseudo-random cryptographic generator algorithm with a symmetric key, based on chaotic functions, is proposed. Moreover, the algorithm exploits dynamic simplicity and synchronization to generate encryption sub-keys using unpredictable seeds, extracted from a chaotic zone, in order to increase their level of randomness. Also, it is applied to a simulated electrical energy consumption signal and implemented on a prototype, using low hardware resources, to measure physical variables; hence, the unpredictability degree was statistically analyzed using the resulting cryptogram. It is shown that the pseudo-random sequences produced by the cryptographic key generator have acceptable properties with respect to randomness, which are validated in this paper using National Institute of Standards and Technology (NIST) statistical tests. To complement the evaluation of the encrypted data, the Lena image is coded and its metrics are compared with those reported in the literature, yielding some useful results