An Effective Low Power Ring Oscillator Based All Digital Phase Locked Loop

The All digital phase-locked loops (ADPLL) widely employed in the data communication systems including, but not limited to, the implementation of the frequency multiplication and clock synchronization circuits. A phase-interpolator is utilized for power consumption reduction by using TDC in a ring-oscillator in a fractional-N phase-locked loop. A predicted-phase-interpolation method is used to calculate the integer and fractional parts of the frequency-division-ratio and to find two interpolation clocks. The prediction method gives a significant power reduction in the proposed PIFC by enabling the use of low-frequency clocks for phase interpolatio

An arbitrarily skewable multiphase clock generator combining direct interpolation with phase error average

A multiphase clock generator based on direct phase interpolation is presented. No feedback loop is required. A simple phase interpolation architecture is proposed, in which the two phase-adjacent signals are interpolated by using a series of resistors via inverters' discharging or charging slopes to generate multiphase outputs in a single stage. A phase error averaging circuit is used to correct interphase errors. The multiphase clock generator has been fabricated in a standard 0.35 μm, 3.3 V CMOS process. The measured performance shows it can operate at the input clock frequencies from 300 MHz to 600 MHz and has the rms jitter of 6 ps at 500 MHz