Standard interface definition for avionics data bus systems

Data bus for avionics system of space shuttle, noting functions of interface unit, error detection and recovery, redundancy, and bus control philosoph

An FPGA-based 77 GHzs RADAR signal processing system for automotive collision avoidance

An FPGA implementable Verilog HDL based signal processing algorithm has been developed to detect the range and velocity of target vehicles using a MEMS based 77 GHz LFMCW long range automotive radar. The algorithm generates a tuning voltage to control a GaAs based VCO to produce a triangular chirp signal, controls the operation of MEMS components, and finally processes the IF signal to determine the range and veolicty of the detected targets. The Verilog HDL code has been developed targeting the Xilinx Virtex-5 SX50T FPGA. The developed algorithm enables the MEMS radar to detect 24 targets in an optimum timespan of 6.42 ms in the range of 0.4 to 200 m with a range resolution of 0.19 m and a maximum range error 0.25 m. A maximum relative velocity of ±300 km/h can be determined with a velocity resolution in HDL of 0.95 m/s and a maximum velocity error of 0.83 m/s with a sweep duration of 1 ms

The 30/20 GHz flight experiment system, phase 2. Volume 2: Experiment system description

A detailed technical description of the 30/20 GHz flight experiment system is presented. The overall communication system is described with performance analyses, communication operations, and experiment plans. Hardware descriptions of the payload are given with the tradeoff studies that led to the final design. The spacecraft bus which carries the payload is discussed and its interface with the launch vehicle system is described. Finally, the hardwares and the operations of the terrestrial segment are presented

A Sub-Centimeter Ranging Precision LIDAR Sensor Prototype Based on ILO-TDC

This thesis introduces a high-resolution light detection and ranging (LIDAR) sensor system-on-a-chip (SoC) that performs sub-centimeter ranging precision and maximally 124-meter ranging distance. With off-chip connected avalanche photodiodes (APDs), the time-of-flight (ToF) are resolved through 31×1 time-correlated single photon counting (TCSPC) channels. Embedded time-to-digital converters (TDCs) support 52-ps time resolution and 14-bit dynamic range. A novel injection-locked oscillator (ILO) based TDC are proposed to minimize the power of fine TDC clock distribution, and improve time precision. The global PVT variation among ILO clock distribution is calibrated by an on-chip phase-looked-loop (PLL) that assures a reliable counting performance over wide operating range. The proposed LIDAR sensor is designed, fabricated, and tested in the 65nm CMOS technology. Whole SoC consumes 37mW and each TDC channel consumes 788μW at nominal operation. The proposed TDC design achieved single-shot precision of 38.5 ps, channel uniformity of 14 ps, and DNL/INL of 0.56/1.56 LSB, respectively. The performance of proposed ILO-TDC makes it an excellent candidate for global counting TCSPC in automotive LIDAR

Design Techniques for High Pin Efficiency Wireline Transceivers

While the majority of wireline research investigates bandwidth improvement and how to overcome the high channel loss, pin efficiency is also critical in high-performance wireline applications. This dissertation proposes two different implementations for high pin efficiency wireline transceivers. The first prototype achieves twice pin efficiency than unidirectional signaling, which is 32Gb/s simultaneous bidirectional transceiver supporting transmission and reception on the same channel at the same time. It includes an efficient low-swing voltage-mode driver with an R-gm hybrid for signal separation, combining the continuous-time-linear-equalizer (CTLE) and echo cancellation (EC) in a single stage, and employing a low-complexity 5/4X CDA system. Support of a wide range of channels is possible with foreground adaptation of the EC finite impulse response (FIR) filter taps with a sign-sign least-mean-square (SSLMS) algorithm. Fabricated in TSMC 28-nm CMOS, the 32Gb/s SBD transceiver occupies $0.09 mm^{2}$ area and achieves 16Gb/s uni-directional and 32Gb/s simultaneous bi-directional signals. 32Gb/s SBD operation consumes 1.83mW/Gb/s with 10.8dB channel loss at Nyquist rate. The second prototype presents an optical transmitter with a quantum-dot (QD) microring laser. This can support wavelength-division multiplexing allowing for high pin efficiency application by packing multiple high-bandwidth signals onto one optical channel. The development QD microring laser model accurately captures the intrinsic photonic high-speed dynamics and allows for the future co-design of the circuits and photonic device. To achieve higher bandwidth than intrinsic one, utilizing both techniques of optical injection locking (OIL) and 2-tap asymmetric Feed-forward equalizer (FFE) can perform 22Gb/s operation with 3.2mW/Gb/s. The first hybrid-integration directly-modulated OIL QD microring laser system is demonstrated

MULTIPAC, a multiple pool processor and computer for a spacecraft central data system, phase 2 Final report

MULTIPAC, multiple pool processor and computer for deep space probe central data syste

Emulation of Narrowband Powerline Data Transmission Channels and Evaluation of PLC Systems

This work proposes advanced emulation of the physical layer behavior of NB-PLC channels and the application of a channel emulator for the evaluation of NB-PLC systems. In addition, test procedures and reference channels are proposed to improve efficiency and accuracy in the system evaluation and classification. This work shows that the channel emulator-based solution opens new ways toward flexible, reliable and technology-independent performance assessment of PLC modems

Studies of methods of pre-launch testing of satellite radar altimeters

The radar altimeter operating in a pulse-limited mode has been successful in charting the ocean surfaces of the Earth. The scientific community, in a drive to map rougher terrain, have adopted the same principle. However in order to overcome the problem of slope- induced error, the range window may be widened or narrowed in accordance with the surface roughness. The ERS-1 altimeter included a second range window for operation over ice, but which had to be controlled by macro-command from the ground. The Advanced Terrain-Tracking Altimeter is a prototype altimeter which has an on-board resolution-switching algorithm, allowing the range window to be changed appropriately. This thesis focuses on methods of pre-launch testing of advanced radar altimeters. The early chapters review some of the calibration and testing methods used for the ERS-1 altimeter, presenting a critical assessment of some of the pre-launch methods. The testing procedure for the Adaptive Terrain-Tracking Altimeter is significantly more complex because of the extra resolution-switching algorithm, and a return signal simulator is identified as an essential element in testing the adaptive resolution prior to launch. The core of the thesis therefore describes a novel method of return signal simulation in which sequences of realistic echoes, from all types of surface, are fed in real time to the prototype altimeter, at the appropriate resolution, with the appropriate fading characteristics, and at the appropriate instant in time. Such a simulator is feasible only if the simulated echo is modelled in the deramp domain (i.e range window space) rather than actual delay time. Then the Fourier Transforms of the echoes, rather than the echoes themselves, are calculated at the full pulse repetition frequency and are stored in a memory. The resolution may then be varied by altering the rate at which the echoes are read out of memory. A prototype Return Signal Simulator is built, tested and shown to be capable of testing the Adaptive Terrain-Tracking Altimeter. A test philosophy is defined to assist the testing of the prototype altimeter, which will be undertaken by British Aerospace. A preliminary analysis, using a software implementation of the return signal simulator and realistic echoes, demonstrated that the Model Free Tracker has a superior tracking performance than the generally preferred Offset Centre Of Gravity tracking algorithm. However both algorithms suffer from problems, and these problems are identified. Finally a new approach to the analysis of the effect of chirp phase errors is presented, which leads to a quantitative expression for the height error resulting from chirp phase distortion. Such an approach can be used to apply a correction to the height estimate, unlike previous approaches which could only be used to set a specification for altimeter design

Fault tolerant programmable digital attitude control electronics study

The attitude control electronics mechanization study to develop a fault tolerant autonomous concept for a three axis system is reported. Programmable digital electronics are compared to general purpose digital computers. The requirements, constraints, and tradeoffs are discussed. It is concluded that: (1) general fault tolerance can be achieved relatively economically, (2) recovery times of less than one second can be obtained, (3) the number of faulty behavior patterns must be limited, and (4) adjoined processes are the best indicators of faulty operation