FPGA Architecture Optimization Using Geometric Programming

Volume 4 No 13 of the periodical Progression. Published November, February, May and August by The Radiant Healing Centre. SPCL PER BT 732 P76 V.1,1932-V.5,193

Methodology for the Accelerated Reliability Analysis and Prognosis of Underground Cables based on FPGA

Dependable electrical power distribution systems demand high reliability levels that cause increased maintenance costs to the utilities. Often, the extra costs are the result of unnecessary maintenance procedures, which can be avoided by monitoring the equipment and predicting the future system evolution by means of statistical methods (prognostics). The present thesis aims at designing accurate methods for predicting the degradation of high and medium voltage underground Cross-Linked Polyethylene (XLPE) cables within an electrical power distribution grid, and predicting their remaining useful life, in order inform maintenance procedures. However, electric power distribution grids are large, components interact with each other, and they degrade with time and use. Solving the statistics of the predictive models of the power grids currently requires long numerical simulations that demand large computational resources and long simulation times even when using advanced parallel architectures. Often, approximate models are used in order to reduce the simulation time and the required resources. In this context, Field Programmable Gate Arrays (FPGAs) can be employed to accelerate the simulation of these stochastic processes. However, the adaptation of the physicsbased degradation models of underground cables for FPGA simulation can be complex. Accordingly, this thesis proposes an FPGA-based framework for the on-line monitoring and prognosis of underground cables based on an electro-thermal degradation model that is adapted for its accelerated simulation in the programmable logic of an FPGA.Energia elektrikoaren banaketa-sare konfidagarriek fidagarritasun maila altuak eskatzen dituzte, eta honek beraien mantenketa kostuen igoera dakar. Kostu hauen arrazoia beraien bizitzan goizegi egiten diren mantenketa prozesuei dagokie askotan, eta hauek eragoztea posible da, ekipamenduaren monitorizazioa eginez eta sistemaren etorkizuneko eboluzioa aurrez estimatuz (prognosia). Tesi honen helburua lurpeko tentsio altu eta ertaineko Cross-Linked Polyethylene (XLPE) kable sistemen eboluzioa eta geratzen zaien bizitza aurreikusiko duten metodo egokiak definitzea izango da, banaketa-sare elektriko baten barruan, ondoren mantenketa prozesu optimo bat ahalbidetuko duena. Hala ere, sistema hauek oso jokaera dinamikoa daukate. Konponente ezberdinek beraien artean elkar eragiten dute eta degradatu egiten dira denboran eta erabileraren ondorioz. Estatistika hauen soluzio analitikoa lortzea ezinezkoa da gaur egun, eta errekurtso asko eskatzen dituen simulazio luzeak behar ditu zenbakizko erantzun bat lortzeko, arkitektura paralelo aurreratuak erabili arren. Field Programmable Gate Array (FPGA)k prozesu estokastiko hauen simulazioa azkartzeko erabil daitezke, baina lurpeko kableen degradazio prozesuen modelo fisikoak FPGA exekuziorako egokitzea konplexua izan daiteke. Beraz, tesi honek FPGA baten logika programagarrian azeleratu ahal izateko egokitua izan den degradazio elektrotermiko modelo baten oinarritutako monitorizazio eta prognosi metodologia bat proposatzen du.Las redes de distribución de energía eléctrica confiables requieren de altos niveles de fiabilidad, que causan un mayor coste de mantenimiento a las empresas distribuidoras. Frecuentemente los costes adicionales son el resultado de procedimientos de mantenimiento innecesarios, que se pueden evitar por medio de la monitorización de los equipos y la predicción de la evolución futura del sistema, por medio de métodos estadísticos (prognosis). La presente tesis pretende desarrollar métodos adecuados para la predicción de la degradación futura de cables de alta y media tensión Cross-Linked Polyethylene (XLPE) soterrados, dentro de una red de distribución eléctrica, y predecir su tiempo de vida restante, para definir una secuencia de mantenimiento óptima. Sin embargo, las redes de distribución eléctrica son grandes, y compuestas por componentes que interactúan entre sí y se degradan con el tiempo y el uso. En la actualidad, resolver estas estadísticas predictivas requieren grandes simulaciones numéricas que requieren de grandes recursos computacionales y largos tiempos de simulación, incluso utilizando arquitecturas paralelas avanzadas. Las Field Programmable Gate Array (FPGA) pueden ser utilizadas para acelerar las simulaciones de estos procesos estocásticos, pero la adaptación de los modelos físicos de degradación de cables soterrados para su simulación en una FPGA puede ser complejo. Así, esta tesis propone el desarrollo de una metodología de monitorización y prognosis cables soterrados, basado en un modelo de degradación electro-térmico que está adaptado para su simulación acelerada en la lógica programable de una FPGA

Hybrid FPGA: Architecture and Interface

Hybrid FPGAs (Field Programmable Gate Arrays) are composed of general-purpose logic resources with different granularities, together with domain-specific coarse-grained units. This thesis proposes a novel hybrid FPGA architecture with embedded coarse-grained Floating Point Units (FPUs) to improve the floating point capability of FPGAs. Based on the proposed hybrid FPGA architecture, we examine three aspects to optimise the speed and area for domain-specific applications. First, we examine the interface between large coarse-grained embedded blocks (EBs) and fine-grained elements in hybrid FPGAs. The interface includes parameters for varying: (1) aspect ratio of EBs, (2) position of the EBs in the FPGA, (3) I/O pins arrangement of EBs, (4) interconnect flexibility of EBs, and (5) location of additional embedded elements such as memory. Second, we examine the interconnect structure for hybrid FPGAs. We investigate how large and highdensity EBs affect the routing demand for hybrid FPGAs over a set of domain-specific applications. We then propose three routing optimisation methods to meet the additional routing demand introduced by large EBs: (1) identifying the best separation distance between EBs, (2) adding routing switches on EBs to increase routing flexibility, and (3) introducing wider channel width near the edge of EBs. We study and compare the trade-offs in delay, area and routability of these three optimisation methods. Finally, we employ common subgraph extraction to determine the number of floating point adders/subtractors, multipliers and wordblocks in the FPUs. The wordblocks include registers and can implement fixed point operations. We study the area, speed and utilisation trade-offs of the selected FPU subgraphs in a set of floating point benchmark circuits. We develop an optimised coarse-grained FPU, taking into account both architectural and system-level issues. Furthermore, we investigate the trade-offs between granularities and performance by composing small FPUs into a large FPU. The results of this thesis would help design a domain-specific hybrid FPGA to meet user requirements, by optimising for speed, area or a combination of speed and area

Memristors for the Curious Outsiders

We present both an overview and a perspective of recent experimental advances and proposed new approaches to performing computation using memristors. A memristor is a 2-terminal passive component with a dynamic resistance depending on an internal parameter. We provide an brief historical introduction, as well as an overview over the physical mechanism that lead to memristive behavior. This review is meant to guide nonpractitioners in the field of memristive circuits and their connection to machine learning and neural computation.Comment: Perpective paper for MDPI Technologies; 43 page

Investigation on the Benefits of Safety Margin Improvement in CANDU Nuclear Power Plant Using an FPGA-based Shutdown System

The relationship between response time and safety margin of CANadian Deuterium Uranium (CANDU) nuclear power plant (NPP) is investigated in this thesis. Implementation of safety shutdown system using Field Programmable Gate Array (FPGA) is explored. The fast data processing capability of FPGAs shortens the response time of CANDU shutdown systems (SDS) such that the impact of accident transient can be reduced. The safety margin, which is closely related to the reactor behavior in the event of an accident, is improved as a result of such a faster shutdown process. Theoretical analysis based on neutron dynamic theory is carried out to establish the fact that a faster shutdown process can mitigate accidental consequences. To provide more realistic test cases from a thermalhydraulic perspective, an industry grade simulation tool known as CATHENA is used to generate comparable accident-shutdown transients for different SDS response times. Results from both verification methods explicitly prove the feasibility of improving the safety margin via faster shutdown process. To demonstrate this concept, a prototype of the proposed faster SDS is constructed. The trip logic of CANDU shutdown system No.1 (SDS1) is converted into a digital hardware design and implemented within chosen FPGA platform. The functionality of the FPGA-based SDS1 is implemented, and the response times are tested and compared to those of the existing CANDU SDS1. The achieved 10.5 ms response time of the FPGA-based SDS1 is again applied to the CATHENA simulation process to quantitatively present the 26.98% improvement in the safety margin. To investigate potential improvement in safety margin by using FPGA technology, hardware-in-the-loop (HIL) simulation is performed by connecting the FPGA-based SDS1 to an NPP training simulator. The 6.26% improvement in safety margin has been verified, based on which a 10% potential power upgrade is discussed as another benefit of applying FPGA technology to CANDU NPPs

Measurements, Models, Systems and Design

531 s.

Stochastic resonance and finite resolution in a network of leaky integrate-and-fire neurons.

This thesis is a study of stochastic resonance (SR) in a discrete implementation of a leaky integrate-and-fire (LIF) neuron network. The aim was to determine if SR can be realised in limited precision discrete systems implemented on digital hardware. How neuronal modelling connects with SR is discussed. Analysis techniques for noisy spike trains are described, ranging from rate coding, statistical measures, and signal processing measures like power spectrum and signal-to-noise ratio (SNR). The main problem in computing spike train power spectra is how to get equi-spaced sample amplitudes given the short duration of spikes relative to their frequency. Three different methods of computing the SNR of a spike train given its power spectrum are described. The main problem is how to separate the power at the frequencies of interest from the noise power as the spike train encodes both noise and the signal of interest. Two models of the LIF neuron were developed, one continuous and one discrete, and the results compared. The discrete model allowed variation of the precision of the simulation values allowing investigation of the effect of precision limitation on SR. The main difference between the two models lies in the evolution of the membrane potential. When both models are allowed to decay from a high start value in the absence of input, the discrete model does not completely discharge while the continuous model discharges to almost zero. The results of simulating the discrete model on an FPGA and the continuous model on a PC showed that SR can be realised in discrete low resolution digital systems. SR was found to be sensitive to the precision of the values in the simulations. For a single neuron, we find that SR increases between 10 bits and 12 bits resolution after which it saturates. For a feed-forward network with multiple input neurons and one output neuron, SR is stronger with more than 6 input neurons and it saturates at a higher resolution. We conclude that stochastic resonance can manifest in discrete systems though to a lesser extent compared to continuous systems

A Comprehensive Workflow for General-Purpose Neural Modeling with Highly Configurable Neuromorphic Hardware Systems

In this paper we present a methodological framework that meets novel requirements emerging from upcoming types of accelerated and highly configurable neuromorphic hardware systems. We describe in detail a device with 45 million programmable and dynamic synapses that is currently under development, and we sketch the conceptual challenges that arise from taking this platform into operation. More specifically, we aim at the establishment of this neuromorphic system as a flexible and neuroscientifically valuable modeling tool that can be used by non-hardware-experts. We consider various functional aspects to be crucial for this purpose, and we introduce a consistent workflow with detailed descriptions of all involved modules that implement the suggested steps: The integration of the hardware interface into the simulator-independent model description language PyNN; a fully automated translation between the PyNN domain and appropriate hardware configurations; an executable specification of the future neuromorphic system that can be seamlessly integrated into this biology-to-hardware mapping process as a test bench for all software layers and possible hardware design modifications; an evaluation scheme that deploys models from a dedicated benchmark library, compares the results generated by virtual or prototype hardware devices with reference software simulations and analyzes the differences. The integration of these components into one hardware-software workflow provides an ecosystem for ongoing preparative studies that support the hardware design process and represents the basis for the maturity of the model-to-hardware mapping software. The functionality and flexibility of the latter is proven with a variety of experimental results