3,199 research outputs found
PeF: Poisson's Equation Based Large-Scale Fixed-Outline Floorplanning
Floorplanning is the first stage of VLSI physical design. An effective
floorplanning engine definitely has positive impact on chip design speed,
quality and performance. In this paper, we present a novel mathematical model
to characterize non-overlapping of modules, and propose a flat fixed-outline
floorplanning algorithm based on the VLSI global placement approach using
Poisson's equation. The algorithm consists of global floorplanning and
legalization phases. In global floorplanning, we redefine the potential energy
of each module based on the novel mathematical model for characterizing
non-overlapping of modules and an analytical solution of Poisson's equation. In
this scheme, the widths of soft modules appear as variables in the energy
function and can be optimized. Moreover, we design a fast approximate
computation scheme for partial derivatives of the potential energy. In
legalization, based on the defined horizontal and vertical constraint graphs,
we eliminate overlaps between modules remained after global floorplanning, by
modifying relative positions of modules. Experiments on the MCNC, GSRC, HB+ and
ami49\_x benchmarks show that, our algorithm improves the average wirelength by
at least 2\% and 5\% on small and large scale benchmarks with certain
whitespace, respectively, compared to state-of-the-art floorplanners
AutoAccel: Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecture
CPU-FPGA heterogeneous architectures are attracting ever-increasing attention
in an attempt to advance computational capabilities and energy efficiency in
today's datacenters. These architectures provide programmers with the ability
to reprogram the FPGAs for flexible acceleration of many workloads.
Nonetheless, this advantage is often overshadowed by the poor programmability
of FPGAs whose programming is conventionally a RTL design practice. Although
recent advances in high-level synthesis (HLS) significantly improve the FPGA
programmability, it still leaves programmers facing the challenge of
identifying the optimal design configuration in a tremendous design space.
This paper aims to address this challenge and pave the path from software
programs towards high-quality FPGA accelerators. Specifically, we first propose
the composable, parallel and pipeline (CPP) microarchitecture as a template of
accelerator designs. Such a well-defined template is able to support efficient
accelerator designs for a broad class of computation kernels, and more
importantly, drastically reduce the design space. Also, we introduce an
analytical model to capture the performance and resource trade-offs among
different design configurations of the CPP microarchitecture, which lays the
foundation for fast design space exploration. On top of the CPP
microarchitecture and its analytical model, we develop the AutoAccel framework
to make the entire accelerator generation automated. AutoAccel accepts a
software program as an input and performs a series of code transformations
based on the result of the analytical-model-based design space exploration to
construct the desired CPP microarchitecture. Our experiments show that the
AutoAccel-generated accelerators outperform their corresponding software
implementations by an average of 72x for a broad class of computation kernels
A Political Method of Evaluating the Education for All Handicapped Children Act of 1975 and the Several Gaps of Gap Analysis
This project can be seen as a collection of architectural explorations that originate from the concept of misunderstanding. The misunderstanding involves an unconscious transformation that can create something new and unexpected and is therefore an important element both in history and in an individual design process. Five examples of misunderstanding from the history of architecture are described in short texts. From each text a drawing is selected that becomes the starting point for a process where translation between alternating digital and analog representation techniques transform the original object, in multiple steps. For each transformation, a text follows, in which the story is reinterpreted and distorted. The last step in this process is a larger physical object that no longer resembles the original drawing, and which, by its ambiguity begins to live its own life. One theme that emerged during the process has been the relationship between architecture and figures or bodies.Detta projekt kan ses som en samling arkitektoniska betraktelser som tar sin utgångspunkt ur begreppet missförstånd. Missförståndet innebär en omedveten transformation som kan skapa något nytt och oväntat och är därför ett viktigt inslag både i historien och i en individuell designprocess. Fem exempel på missförstånd ur arkitekturhistorien beskrivs i korta texter. Utifrån dessa väljs ett antal ritningar som blir utgångspunkt för en process där översättningen mellan omväxlande digitala och analoga representationstekniker förvandlar det ursprungliga objektet i flera steg. För varje transformation följer en text där berättelsen omtolkas och förvrids. Det sista steget i denna process är ett fysiskt objekt i större skala vars gestalt är svår att härleda till den ursprungliga ritningen och som genom sin tvetydighet börjar leva sitt eget eget liv. Ett tema som utkristalliserat sig under processen har varit relationen mellan arkitektur och figurer eller kroppar
FFTPL: An Analytic Placement Algorithm Using Fast Fourier Transform for Density Equalization
We propose a flat nonlinear placement algorithm FFTPL using fast Fourier
transform for density equalization. The placement instance is modeled as an
electrostatic system with the analogy of density cost to the potential energy.
A well-defined Poisson's equation is proposed for gradient and cost
computation. Our placer outperforms state-of-the-art placers with better
solution quality and efficiency
Implementation and optimization of an integrated circuit placement algorithm in parallel environment
Custom Cell Placement Automation for Asynchronous VLSI
Asynchronous Very-Large-Scale-Integration (VLSI) integrated circuits have demonstrated many advantages over their synchronous counterparts, including low power consumption, elastic pipelining, robustness against manufacturing and temperature variations, etc. However, the lack of dedicated electronic design automation (EDA) tools, especially physical layout automation tools, largely limits the adoption of asynchronous circuits. Existing commercial placement tools are optimized for synchronous circuits, and require a standard cell library provided by semiconductor foundries to complete the physical design. The physical layouts of cells in this library have the same height to simplify the placement problem and the power distribution network. Although the standard cell methodology also works for asynchronous designs, the performance is inferior compared with counterparts designed using the full-custom design methodology. To tackle this challenge, we propose a gridded cell layout methodology for asynchronous circuits, in which the cell height and cell width can be any integer multiple of two grid values. The gridded cell approach combines the shape regularity of standard cells with the size flexibility of full-custom layouts. Therefore, this approach can achieve a better space utilization ratio and lower wire length for asynchronous designs. Experiments have shown that the gridded cell placement approach reduces area without impacting the routability. We have also used this placer to tape out a chip in a 65nm process technology, demonstrating that our placer generates design-rule clean results
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