334 research outputs found

    Intrinsically Evolvable Artificial Neural Networks

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    Dedicated hardware implementations of neural networks promise to provide faster, lower power operation when compared to software implementations executing on processors. Unfortunately, most custom hardware implementations do not support intrinsic training of these networks on-chip. The training is typically done using offline software simulations and the obtained network is synthesized and targeted to the hardware offline. The FPGA design presented here facilitates on-chip intrinsic training of artificial neural networks. Block-based neural networks (BbNN), the type of artificial neural networks implemented here, are grid-based networks neuron blocks. These networks are trained using genetic algorithms to simultaneously optimize the network structure and the internal synaptic parameters. The design supports online structure and parameter updates, and is an intrinsically evolvable BbNN platform supporting functional-level hardware evolution. Functional-level evolvable hardware (EHW) uses evolutionary algorithms to evolve interconnections and internal parameters of functional modules in reconfigurable computing systems such as FPGAs. Functional modules can be any hardware modules such as multipliers, adders, and trigonometric functions. In the implementation presented, the functional module is a neuron block. The designed platform is suitable for applications in dynamic environments, and can be adapted and retrained online. The online training capability has been demonstrated using a case study. A performance characterization model for RC implementations of BbNNs has also been presented

    Enhancing Real-time Embedded Image Processing Robustness on Reconfigurable Devices for Critical Applications

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    Nowadays, image processing is increasingly used in several application fields, such as biomedical, aerospace, or automotive. Within these fields, image processing is used to serve both non-critical and critical tasks. As example, in automotive, cameras are becoming key sensors in increasing car safety, driving assistance and driving comfort. They have been employed for infotainment (non-critical), as well as for some driver assistance tasks (critical), such as Forward Collision Avoidance, Intelligent Speed Control, or Pedestrian Detection. The complexity of these algorithms brings a challenge in real-time image processing systems, requiring high computing capacity, usually not available in processors for embedded systems. Hardware acceleration is therefore crucial, and devices such as Field Programmable Gate Arrays (FPGAs) best fit the growing demand of computational capabilities. These devices can assist embedded processors by significantly speeding-up computationally intensive software algorithms. Moreover, critical applications introduce strict requirements not only from the real-time constraints, but also from the device reliability and algorithm robustness points of view. Technology scaling is highlighting reliability problems related to aging phenomena, and to the increasing sensitivity of digital devices to external radiation events that can cause transient or even permanent faults. These faults can lead to wrong information processed or, in the worst case, to a dangerous system failure. In this context, the reconfigurable nature of FPGA devices can be exploited to increase the system reliability and robustness by leveraging Dynamic Partial Reconfiguration features. The research work presented in this thesis focuses on the development of techniques for implementing efficient and robust real-time embedded image processing hardware accelerators and systems for mission-critical applications. Three main challenges have been faced and will be discussed, along with proposed solutions, throughout the thesis: (i) achieving real-time performances, (ii) enhancing algorithm robustness, and (iii) increasing overall system's dependability. In order to ensure real-time performances, efficient FPGA-based hardware accelerators implementing selected image processing algorithms have been developed. Functionalities offered by the target technology, and algorithm's characteristics have been constantly taken into account while designing such accelerators, in order to efficiently tailor algorithm's operations to available hardware resources. On the other hand, the key idea for increasing image processing algorithms' robustness is to introduce self-adaptivity features at algorithm level, in order to maintain constant, or improve, the quality of results for a wide range of input conditions, that are not always fully predictable at design-time (e.g., noise level variations). This has been accomplished by measuring at run-time some characteristics of the input images, and then tuning the algorithm parameters based on such estimations. Dynamic reconfiguration features of modern reconfigurable FPGA have been extensively exploited in order to integrate run-time adaptivity into the designed hardware accelerators. Tools and methodologies have been also developed in order to increase the overall system dependability during reconfiguration processes, thus providing safe run-time adaptation mechanisms. In addition, taking into account the target technology and the environments in which the developed hardware accelerators and systems may be employed, dependability issues have been analyzed, leading to the development of a platform for quickly assessing the reliability and characterizing the behavior of hardware accelerators implemented on reconfigurable FPGAs when they are affected by such faults

    New Design Techniques for Dynamic Reconfigurable Architectures

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    L'abstract è presente nell'allegato / the abstract is in the attachmen

    The Fifth NASA Symposium on VLSI Design

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    The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design

    Design, construction, and test of the Gas Pixel Detectors for the IXPE mission

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    Due to be launched in late 2021, the Imaging X-Ray Polarimetry Explorer (IXPE) is a NASA Small Explorer mission designed to perform polarization measurements in the 2-8 keV band, complemented with imaging, spectroscopy and timing capabilities. At the heart of the focal plane is a set of three polarization-sensitive Gas Pixel Detectors (GPD), each based on a custom ASIC acting as a charge-collecting anode. In this paper we shall review the design, manufacturing, and test of the IXPE focal-plane detectors, with particular emphasis on the connection between the science drivers, the performance metrics and the operational aspects. We shall present a thorough characterization of the GPDs in terms of effective noise, trigger efficiency, dead time, uniformity of response, and spectral and polarimetric performance. In addition, we shall discuss in detail a number of instrumental effects that are relevant for high-level science analysis -- particularly as far as the response to unpolarized radiation and the stability in time are concerned.Comment: To be published in Astroparticle Physic

    The 1992 4th NASA SERC Symposium on VLSI Design

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    Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design

    Implementation of a X-mode multichannel edge density profile reflectometer for the new ICRH antenna on ASDEX Upgrade

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    Ion cyclotron resonance heating (ICRH) is one of the main heating mechanisms for nuclear fusion plas- mas. However, studying the effects of ICRH operation, such as power coupling efficiency and convective transport, requires the measurement of the local edge plasma density profiles. Two new three-strap an- tennas were designed to reduce tungsten impurity release during operation, and installed on ASDEX Upgrade. One of these ICRH antennas embedded ten pairs of small microwave pyramidal horn anten- nas. In this thesis, a new multichannel X-mode microwave reflectometry diagnostic was developed to use these embedded antennas to simultaneously measure the edge electron density profiles in front of the bottom, middle and top regions of the radiating surface of the ICRH antenna. Microwave reflectome- try is a radar technique that measures the round trip delay of probing waves that are reflected at specific cutoff layers, depending on the probing wave frequency, plasma density and local magnetic field. This diagnostic uses a coherent heterodyne quadrature detection architecture and probes the plasma in the range 40-68 GHz to measure plasma edge electron densities up to 2×1019 m-3, with magnetic fields between 1.85 T and 2.7 T, and a repetition interval as low as 25 μs. This work details the implementa- tion and commissioning of the diagnostic, including the calibration of the microwave hardware and the analysis of the raw reflectometry measurements. We study the automatic initialization of the X-mode upper cutoff measurement, which is the main source of error in X-mode density profile reconstruction. Two first fringe estimation algorithms were developed: one based on amplitude and spectral information and another using a neural network model to recognize the first fringe location from spectrogram data. Kalman filters are used to improve radial measurement uncertainty to less than 1 cm. To validate the diagnostic, we compared the density profile measurements with other electron density diagnostics on ASDEX Upgrade, and observed typical plasma phenomena like the L-H transition and ELM activity. The experimental density profile results were used to corroborate ICRH power coupling simulations under different gas puffing conditions and to observe poloidal convective transport during ICRH operation

    Charting NeuLAND: Towards multi-neutron reconstruction with the New Large Area Neutron Detector and The virtual γ-ray spectrometer G4Horus

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    This thesis presents work on the New Large Area Neutron Detector NeuLAND, which will be used at the upcoming Facility for Antiproton and Ion Research (FAIR), Germany. Assembly steps for detector modules are described, followed by experiments performed with the NeuLAND Demonstrator in Japan. The detector is also assembled virtually for Monte Carlo simulations, including a conversion process from energy depositions to experimental look-alike events. This detector response is in good agreement with experimental data from Japan. Performance and behavior of newly developed reconstruction methods are mapped out for different detector sizes. These algorithms can reconstruct multiplicity and primary interaction points for many incoming neutrons. In addition, the groundwork for event reconstruction with neural networks is laid. In the second part, the Geant4 application G4Horus is presented, which implements a virtual version of the HORUS γ-ray spectrometer used at the Institute for Nuclear Physics, University of Cologne. The high purity germanium (HPGe) detectors in this spectrometer are often used to measure γ-rays from 5 MeV to 10 MeV. No standardized calibration sources are available at these energies, and the efficiency calibration is challenging. G4Horus alleviates this problem with easy to use efficiency simulations. More complex experiments with particle detectors and respective data analysis procedures can be understood and improved with matching simulations. Here, G4Horus provides listmode data with simulated particle-γ coincidences

    Präzise Zeit- und Energiemessungen mit Hochgranularen, Hadronischen Kalorimetern

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    This thesis presents an analysis of the time structure of hadronic showers with a highly granular, hadronic calorimeter prototype (AHCAL) developed by the CALICE collaboration. It is explored on simulated data to what extend hit time measurements on cell-level can improve the energy reconstruction in such a calorimeter. Furthermore, a neural network setup for the energy reconstruction in the AHCAL is developed, using the shower profile of hadronic showers to enhance the energy resolution.In dieser Arbeit wird die Zeitstruktur von hadronischen Teilchenschauern in einem von der CALICE Kollaboration entwickelten, hochgranularen, hadronischen Kalorimeter Prototypen (AHCAL) analysiert. Anhand simulierter Daten wird die Möglichkeit untersucht diese Zeitinformationen für eine verbesserte Energierekonstruktion zu benutzen. Zusätzlich wird ein Ansatz zur Energierekonstruktion im AHCAL auf Basis eines neuronalen Netzwerkes entwickelt
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