Architectural Alternatives to Implement High-Performance Delta-Sigma Modulators

RÉSUMÉ Le besoin d’appareils portatifs, de téléphones intelligents et de systèmes microélectroniques implantables médicaux s’accroît remarquablement. Cependant, l’optimisation de l’alimentation de tous ces appareils électroniques portables est l’un des principaux défis en raison du manque de piles à grande capacité utilisées pour les alimenter. C’est un fait bien établi que le convertisseur analogique-numérique (CAN) est l’un des blocs les plus critiques de ces appareils et qu’il doit convertir efficacement les signaux analogiques au monde numérique pour effectuer un post-traitement tel que l’extraction de caractéristiques. Parmi les différents types de CAN, les modulateurs Delta Sigma (��M) ont été utilisés dans ces appareils en raison des fonctionnalités alléchantes qu’ils offrent. En raison du suréchantillonnage et pour éloigner le bruit de la bande d’intérêt, un CAN haute résolution peut être obtenu avec les architectures ��. Il offre également un compromis entre la fréquence d’échantillonnage et la résolution, tout en offrant une architecture programmable pour réaliser un CAN flexible. Ces CAN peuvent être implémentés avec des blocs analogiques de faible précision. De plus, ils peuvent être efficacement optimisés au niveau de l’architecture et circuits correspondants. Cette dernière caractéristique a été une motivation pour proposer différentes architectures au fil des ans. Cette thèse contribue à ce sujet en explorant de nouvelles architectures pour optimiser la structure ��M en termes de résolution, de consommation d’énergie et de surface de silicium. Des soucis particuliers doivent également être pris en compte pour faciliter la mise en œuvre du ��M. D’autre part, les nouveaux procédés CMOS de conception et fabrication apportent des améliorations remarquables en termes de vitesse, de taille et de consommation d’énergie lors de la mise en œuvre de circuits numériques. Une telle mise à l’échelle agressive des procédés, rend la conception de blocs analogiques tel que un amplificateur de transconductance opérationnel (OTA), difficile. Par conséquent, des soins spéciaux sont également pris en compte dans cette thèse pour surmonter les problèmes énumérés. Ayant mentionné ci-dessus que cette thèse est principalement composée de deux parties principales. La première concerne les nouvelles architectures implémentées en mode de tension et la seconde partie contient une nouvelle architecture réalisée en mode hybride tension et temps.----------ABSTRACT The need for hand-held devices, smart-phones and medical implantable microelectronic sys-tems, is remarkably growing up. However, keeping all these electronic devices power optimized is one of the main challenges due to the lack of long life-time batteries utilized to power them up. It is a well-established fact that analog-to-digital converter (ADC) is one of the most critical building blocks of such devices and it needs to efficiently convert analog signals to the digital world to perform post processing such as channelizing, feature extraction, etc. Among various type of ADCs, Delta Sigma Modulators (��Ms) have been widely used in those devices due to the tempting features they offer. In fact, due to oversampling and noise-shaping technique a high-resolution ADC can be achieved with �� architectures. It also offers a compromise between sampling frequency and resolution while providing a highly-programmable approach to realize an ADC. Moreover, such ADCs can be implemented with low-precision analog blocks. Last but not the least, they are capable of being effectively power optimized at both architectural and circuit levels. The latter has been a motivation to proposed different architectures over the years.This thesis contributes to this topic by exploring new architectures to effectively optimize the ��M structure in terms of resolution, power consumption and chip area. Special cares must also be taken into account to ease the implementation of the ��M. On the other hand, advanced node CMOS processes bring remarkable improvements in terms of speed, size and power consumption while implementing digital circuits. Such an aggressive process scaling, however, make the design of analog blocks, e.g. operational transconductance amplifiers (OTAs), cumbersome. Therefore, special cares are also taken into account in this thesis to overcome the mentioned issues. Having had above mentioned discussion, this thesis is mainly split in two main categories. First category addresses new architectures implemented in a pure voltage domain and the second category contains new architecture realized in a hybrid voltage and time domain. In doing so, the thesis first focuses on a switched-capacitor implementation of a ��M while presenting an architectural solution to overcome the limitations of the previous approaches. This limitations include a power hungry adder in a conventional feed-forward topology as well as power hungry OTAs

Interface Circuits for Microsensor Integrated Systems

ca. 200 words; this text will present the book in all promotional forms (e.g. flyers). Please describe the book in straightforward and consumer-friendly terms. [Recent advances in sensing technologies, especially those for Microsensor Integrated Systems, have led to several new commercial applications. Among these, low voltage and low power circuit architectures have gained growing attention, being suitable for portable long battery life devices. The aim is to improve the performances of actual interface circuits and systems, both in terms of voltage mode and current mode, in order to overcome the potential problems due to technology scaling and different technology integrations. Related problems, especially those concerning parasitics, lead to a severe interface design attention, especially concerning the analog front-end and novel and smart architecture must be explored and tested, both at simulation and prototype level. Moreover, the growing demand for autonomous systems gets even harder the interface design due to the need of energy-aware cost-effective circuit interfaces integrating, where possible, energy harvesting solutions. The objective of this Special Issue is to explore the potential solutions to overcome actual limitations in sensor interface circuits and systems, especially those for low voltage and low power Microsensor Integrated Systems. The present Special Issue aims to present and highlight the advances and the latest novel and emergent results on this topic, showing best practices, implementations and applications. The Guest Editors invite to submit original research contributions dealing with sensor interfacing related to this specific topic. Additionally, application oriented and review papers are encouraged.

Linearization of Time-encoded ADCs Architectures for Smart MEMS Sensors in Low Power CMOS Technology

Mención Internacional en el título de doctorIn the last few years, the development of mobile technologies and machine learning applications has increased the demand of MEMS-based digital microphones. Mobile devices have several microphones enabling noise canceling, acoustic beamforming and speech recognition. With the development of machine learning applications the interest to integrate sensors with neural networks has increased. This has driven the interest to develop digital microphones in nanometer CMOS nodes where the microphone analog-front end and digital processing, potentially including neural networks, is integrated on the same chip. Traditionally, analog-to-digital converters (ADCs) in digital microphones have been implemented using high order Sigma-Delta modulators. The most common technique to implement these high order Sigma-Selta modulators is switchedcapacitor CMOS circuits. Recently, to reduce power consumption and make them more suitable for tasks that require always-on operation, such as keyword recognition, switched-capacitor circuits have been improved using inverter-based operational amplifier integrators. Alternatively, switched-capacitor based Sigma- Delta modulators have been replaced by continuous time Sigma-Delta converters. Nevertheless, in both implementations the input signal is voltage encoded across the modulator, making the integration in smaller CMOS nodes more challenging due to the reduced voltage supply. An alternative technique consists on encoding the input signal on time (or frequency) instead of voltage. This is what time-encoded converters do. Lately, time-encoding converters have gained popularity as they are more suitable to nanometer CMOS nodes than Sigma-Delta converters. Among the ones that have drawn more interest we find voltage-controlled oscillator based ADCs (VCOADCs). VCO-ADCs can be implemented using CMOS inverter based ring oscillators (RO) and digital circuitry. They also show noise-shaping properties. This makes them a very interesting alternative for implementation of ADCs in nanometer CMOS nodes. Nevertheless, two main circuit impairments are present in VCO-ADCs, and both come from the oscillator non-idealities. The first of them is the oscillator phase noise, that reduces the resolution of the ADC. The second is the non-linear tuning curve of the oscillator, that results in harmonic distortion at medium to high input amplitudes. In this thesis we analyze the use of time encoding ADCs for MEMS microphones with special focus on ring oscillator based ADCs (RO-ADCs). Firstly, we study the use of a dual-slope based SAR noise shaped quantizer (SAR-NSQ) in sigma-delta loops. This quantizer adds and extra level of noise-shaping to the modulator, improving the resolution. The quantizer is explained, and equations for the noise transfer function (NTF) of a third order sigma-delta using a second order filter and the NSQ are presented. Secondly, we move our attention to the topic of RO-ADCs. We present a high dynamic range MEMS microphone 130nm CMOS chip based on an open-loop VCO-ADC. This dissertation shows the implementation of the analog front-end that includes the oscillator and the MEMS interface, with a focus on achieving low power consumption with low noise and a high dynamic range. The digital circuitry is left to be explained by the coauthor of the chip in his dissertation. The chip achieves a 80dBA peak SNDR and 108dB dynamic range with a THD of 1.5% at 128 dBSPL with a power consumption of 438μW. After that, we analyze the use of a frequency-dependent-resistor (FDR) to implement an unsampled feedback loop around the oscillator. The objective is to reduce distortion. Additionally phase noise mitigation is achieved. A first topology including an operational amplifier to increase the loop gain is analyzed. The design is silicon proven in a 130 nm CMOS chip that achieves a 84 dBA peak SNDR with an analog power consumption of 600μW. A second topology without the operational amplifier is also analyzed. Two chips are designed with this topology. The first chip in 130 nm CMOS is a full VCO-ADC including the frequencyto- digital converter (F2D). This chip achieves a peak SNDR of 76.6 dBA with a power consumption of 482μW. The second chip includes only the oscillator and is implemented in 55nm CMOS. The peak SNDR is 78.15 dBA and the analog power consumption is 153μW. To finish this thesis, two circuits that use an FDR with a ring oscillator are presented. The first is a capacity-to-digital converter (CDC). The second is a filter made with an FDR and an oscillator intended for voice activity detection tasks (VAD).En los últimos años, el desarrollo de las tecnologías móviles y las aplicaciones de machine-learning han aumentado la demanda de micrófonos digitales basados en MEMS. Los dipositivos móviles tienen varios micrófonos que permiten la cancelación de ruido, el beamforming o conformación de haces y el reconocimiento de voz. Con el desarrollo de aplicaciones de aprendizaje automático, el interés por integrar sensores con redes neuronales ha aumentado. Esto ha impulsado el interés por desarrollar micrófonos digitales en nodos CMOS nanométricos donde el front-end analógico y el procesamiento digital del micrófono, que puede incluir redes neuronales, está integrado en el mismo chip. Tradicionalmente, los convertidores analógicos-digitales (ADC) en micrófonos digitales han sido implementados utilizando moduladores Sigma-Delta de orden elevado. La técnica más común para implementar estos moduladores Sigma- Delta es el uso de circuitos CMOS de capacidades conmutadas. Recientemente, para reducir el consumo de potencia y hacerlos más adecuados para las tareas que requieren una operación continua, como el reconocimiento de palabras clave, los convertidores Sigma-Delta de capacidades conmutadas has sido mejorados con el uso de integradores implementados con amplificadores operacionales basados en inversores CMOS. Alternativamente, los Sigma-Delta de capacidades conmutadas han sido reemplazados por moduladores en tiempo continuo. No obstante, en ambas implementaciones, la señal de entrada es codificada en voltaje durante el proceso de conversión, lo que hace que la integración en nodos CMOS más pequeños sea complicada debido a la menor tensión de alimentación. Una técnica alternativa consiste en codificar la señal de entrada en tiempo (o frecuencia) en lugar de tensión. Esto es lo que hacen los convertidores de codificación temporal. Recientemente, los convertidores de codificación temporal han ganado popularidad ya que son más adecuados para nodos CMOS nanométricos que los convertidores Sigma-Delta. Entre los que más interés han despertado encontramos los ADCs basados en osciladores controlados por tensión (VCO-ADC). Los VCO-ADC se pueden implementar usando osciladores en anillo (RO) implementados con inversores CMOS y circuitos digitales. Esta familia de convertidores también tiene conformado de ruido. Esto los convierte en una alternativa muy interesante para la implementación de convertidores en nodos CMOS nanométricos. Sin embargo, dos problemas principales están presentes en este tipo de ADCs debidos ambos a las no idealidades del oscilador. El primero de los problemas es la presencia de ruido de fase en el oscilador, lo que reduce la resolución del ADC. El segundo es la curva de conversion voltaje-frecuencia no lineal del oscilador, lo que causa distorsión a amplitudes medias y altas. En esta tesis analizamos el uso de ADCs de codificación temporal para micrófonos MEMS, con especial interés en ADCS basados en osciladores de anillo (RO-ADC). En primer lugar, estudiamos el uso de un cuantificador SAR con conformado de ruido (SAR-NSQ) en moduladores Sigma-Delta. Este cuantificador agrega un orden adicional de conformado de ruido al modulador, mejorando la resolución. En este documento se explica el cuantificador y obtienen las ecuaciones para la función de transferencia de ruido (NTF) de un sigma-delta de tercer orden usando un filtro de segundo orden y el NSQ. En segundo lugar, dirigimos nuestra atención al tema de los RO-ADC. Presentamos el chip de un micrófono MEMS de alto rango dinámico en CMOS de 130 nm basado en un VCO-ADC de bucle abierto. En esta tesis se explica la implementación del front-end analógico que incluye el oscilador y la interfaz con el MEMS. Esta implementación se ha llevado a cabo con el objetivo de lograr un bajo consumo de potencia, un bajo nivel de ruido y un alto rango dinámico. La descripción del back-end digital se deja para la tesis del couator del chip. La SNDR de pico del chip es de 80dBA y el rango dinámico de 108dB con una THD de 1,5% a 128 dBSPL y un consumo de potencia de 438μW. Finalmente, se analiza el uso de una resistencia dependiente de frecuencia (FDR) para implementar un bucle de realimentación no muestreado alrededor del oscilador. El objetivo es reducir la distorsión. Además, también se logra la mitigación del ruido de fase del oscilador. Se analyza una primera topologia de realimentación incluyendo un amplificador operacional para incrementar la ganancia de bucle. Este diseño se prueba en silicio en un chip CMOS de 130nm que logra un pico de SNDR de 84 dBA con un consumo de potencia de 600μW en la parte analógica. Seguidamente, se analiza una segunda topología sin el amplificador operacional. Se fabrican y miden dos chips diseñados con esta topologia. El primero de ellos en CMOS de 130 nm es un VCO-ADC completo que incluye el convertidor de frecuencia a digital (F2D). Este chip alcanza un pico SNDR de 76,6 dBA con un consumo de potencia de 482μW. El segundo incluye solo el oscilador y está implementado en CMOS de 55nm. El pico SNDR es 78.15 dBA y el el consumo de potencia analógica es de 153μW. Para cerrar esta tesis, se presentan dos circuitos que usan la FDR con un oscilador en anillo. El primero es un convertidor de capacidad a digital (CDC). El segundo es un filtro realizado con una FDR y un oscilador, enfocado a tareas de detección de voz (VAD).Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Antonio Jesús Torralba Silgado.- Secretaria: María Luisa López Vallejo.- Vocal: Pieter Rombout

Digital Friendly Continuous-Time Delta-Sigma Analog-to-Digital Converters

Conventional Delta-Sigma analog-to-digital converters (ADCs) utilize operational transconductance amplifiers (OTAs) in their loop filter implementation followed by multi-bit voltage domain quantizers. As CMOS integrated circuit technology scales to smaller geometries, the minimum transistor length and the intrinsic gain of the transistors decrease. Moreover, with process scaling the voltage headroom decreases as well. Therefore, designing OTAs in advanced CMOS processes is becoming increasingly difficult. Additionally, multibit quantizers are becoming more difficult to design due to the decreased voltage headroom and the challenges of low offset and noise requirements. In this thesis, alternative digital solutions are introduced to replace traditional analog blocks. In the proposed solutions, compressed voltage-domain processing is shifted to the time-domain which benefits from process scaling as the transistors scale down in size and become faster. First, a novel highly linear VCO-based 1-1 multi stage noise shaping (MASH) delta-sigma ADC structure is presented. The proposed architecture does not require any OTA-based analog integrators or integrating capacitors. Second-order noise shaping is achieved by using a VCO as an integrator in the feedback loop of the first stage and an open loop VCO quantizer in the second stage. A prototype was fabricated in a 65nm CMOS process and achieves 79.7 dB SNDR for a 2MHz signal bandwidth. Second, a novel time-domain phase quantization noise extraction for a VCO-based quantizer is introduced. This technique is independent of the OSR and the input signal amplitude of the VCO-based quantizer making it attractive for higher bandwidth applications. Using this technique, a novel 0-1-1 MASH ADC is presented. The first stage is implemented using a 4-bit SAR ADC. The second and the third stages use a VCO-based quantizer (VCOQ). Behavioral simulation results con�rm second-order noise shaping with a 75dB SNDR for an OSR of 20

LOW POWER AND HIGH SIGNAL TO NOISE RATIO BIO-MEDICAL AFE DESIGN TECHNIQUES

The research work described in this thesis was focused on finding novel techniques to implement a low-power and noise Bio-Medical Analog Front End (BMEF) circuit technique to enable high-quality Electrocardiography (ECG) sensing. Usually, an ECG signal and several bio-medical signals are sensed from the human body through a pair of electrodes. The electrical characteristics of the very small amplitude (1u-10mV) signals are corrupted by random noise and have a significant dc offset. 50/60Hz power supply coupling noise is one of the biggest cross-talk signals compared to the thermally generated random noise. These signals are even AFE composed of an Instrumentation Amplifier (IA), which will have a better Common Mode rejection ratio (CMRR). The main function of the AFE is to convert the weak electrical Signal into large signals whose amplitude is large enough for an Analog Digital Converter (ADC) to detect without having any errors. A Variable Gain Amplifier (VGA) is sometimes required to adjust signal amplitude to maintain the dynamic range of the ADC. Also, the Bio-medical transceiver needs an accurate and temperature-independent reference voltage and current for the ADC, commonly known as Bandgap Reference Circuit (BGR). These circuits need to consume as low power as possible to enable these circuits to be powered from the battery. The work started with analysing the existing circuit techniques for the circuits mentioned above and finding the key important improvements required to reach the target specifications. Previously proposed IA is generated based on voltage mode signal processing. To improve the CMRR (119dB), we proposed a current mode-based IA with an embedded DC cancellation technique. State-of-the-art VGA circuits were built based on the degeneration principle of the differential pair, which will enable the variable gain purpose, but none of these techniques discussed linearity improvement, which is very important in modern CMOS technologies. This work enhances the total Harmonic distortion (THD) by 21dB in the worst case by exploiting the feedback techniques around the differential pair. Also, this work proposes a low power curvature compensated bandgap with 2ppm/0C temperature sensitivity while consuming 12.5uW power from a 1.2V dc power supply. All circuits were built in 45nm TSMC-CMOS technology and simulated with all the performance metrics with Cadence (spectre) simulator. The circuit layout was carried out to study post-layout parasitic effect sensitivity

Next generation analog-to-digital conversion using time-based encoding and digital synthesis techniques

The internet-of-things is a growing market segment which is based on an arrayof portable communication devices with high power efficiency. Advanced semiconductortechnology can easily improve their digital performance, but the samecannot be said for the analog blocks which are vital to their operation. Highperformance analog circuits continue to use conventional design techniques andarchitectures at the expense of power efficiency. Deeply scaled CMOS exaggeratesthis trade-off, opening the door for novel system techniques that take advantage ofthe digital nature of sub-micron transistors. This research focuses on two highlydigital ADCs which can mitigate the short channel effects of limited output swingand low intrinsic gain while also benefiting from process scaling.First, a multi-domain ADC is used to perform quantization on both voltageand time domain signals, relaxing the power-performance trade-off. This hybridapproach can lead to a high resolution, high efficiency data converter in scaledprocess. A prototype ADC was fabricated in 180nm CMOS, showing an SNDRof 73 dB, operating at 20 MHz sampling frequency, with a power consumption of1.28 mW.Next, an automated synthesis process is used to automatically generate a highspeed VCO-based quantizer from verilog code. Stochastic spatial averaging iscombined with a high speed open-loop noise-shaping quantizer to provide enhancedresolution in the presence of device mismatch. Simulation results of a prototypeADC in 180nm CMOS shows an SNDR of 49 dB, operating at 800 MHz samplingfrequency and 50 MHz signal bandwidth.Keywords: data converter, synthesis, verilog, ADC, SAR, TD

Interfaces neuronales CMOS haute résolution pour l'électrophysiologie et l'optogénétique en boucle fermée

L’avenir de la recherche sur les maladies du cerveau repose sur le développement de nouvelles technologies qui permettront de comprendre comment cet organe si complexe traite, intègre et transfère l’information. Parmi celles-ci, l’optogénétique est une technologie révolutionnaire qui permet d’utiliser de la lumière afin d’activer sélectivement les neurones du cortex d’animaux transgéniques pour observer leur effet dans un vaste réseau biologique. Ce cadre expérimental repose typiquement sur l’observation de l’activité neuronale de souris transgéniques, car elles peuvent exprimer une grande variété de gènes et de maladies et qu’elles sont peu couteuses. Toutefois, la plupart des appareils de mesure ou de stimulation optogénétique disponible ne sont pas appropriés, car ils sont câblés, trop lourds et/ou trop simplistes. Malheureusement, peu de systèmes sans fil existent, et ces derniers sont grandement limités par la bande passante requise pour transmettre les données neuronales, et ils ne fournissent pas de stimulation optogénétique multicanal afin de stimuler et observer plusieurs régions du cerveau. Dans les dispositifs actuels, l’interprétation des données neuronales est effectuée ex situ, alors que la recherche bénéficierait grandement de systèmes sans fil assez intelligents pour interpréter et stimuler les neurones en boucle fermée, in situ. Le but de ce projet de recherche est de concevoir des circuits analogiques-numériques d’acquisition et de traitement des signaux neuronaux, des algorithmes d’analyse et de traitement de ces signaux et des systèmes electro-optiques miniatures et sans fil pour : i) Mener des expériences combinant l’enregistrement neuronal et l’optogénétique multicanal haute résolution avec des animaux libres de leurs mouvements. ii) Mener des expériences optogénétiques synchronisées avec l’observation, c.-à-d. en boucle fermée, chez des animaux libres de leurs mouvements. iii) Réduire la taille, le poids et la consommation énergétique des systèmes optogénétiques sans fil afin de minimiser l’impact de la recherche chez de petits animaux. Ce projet est en 3 phases, et ses principales contributions ont été rapportées dans dix conférences internationales (ISSCC, ISCAS, EMBC, etc.) et quatre articles de journaux publiés ou soumis, ainsi que dans un brevet et deux divulgations. La conception d’un système optogénétique haute résolution pose plusieurs défis importants. Notamment, puisque les signaux neuronaux ont un contenu fréquentiel élevé (_10 kHz), le nombre de canaux sous observation est limité par la bande passante des transmetteurs sans fil (2-4 canaux en général). Ainsi, la première phase du projet a visé le développement d’algorithmes de compression des signaux neuronaux et leur intégration dans un système optogénétique sans fil miniature et léger (2.8 g) haute résolution possédant 32 canaux d’acquisition et 32 canaux de stimulation optique. Le système détecte, compresse et transmet les formes d’onde des potentiels d’action (PA) produits par les neurones avec un field programmable gate array (FPGA) embarqué à faible consommation énergétique. Ce processeur implémente un algorithme de détection des PAs basé sur un seuillage adaptatif, ce qui permet de compresser les signaux en transmettant seulement les formes détectées. Chaque PA est davantage compressé par une transformée en ondelette discrète (DWT) de type Symmlet-2 suivie d’une technique de discrimination et de requantification dynamique des coefficients. Les résultats obtenus démontrent que cet algorithme est plus robuste que les méthodes existantes tout en permettant de reconstruire les signaux compressés avec une meilleure qualité (SNDR moyen de 25 dB _ 5% pour un taux de compression (CR) de 4.2). Avec la détection, des CR supérieurs à 500 sont rapportés lors de la validation in vivo. L’utilisation de composantes commerciales dans des systèmes optogénétiques sans fil augmentela taille et la consommation énergétique, en plus de ne pas être optimisée pour cette application. La seconde phase du projet a permis de concevoir un système sur puce (SoC) complementary metal oxide semiconductor (CMOS) pour faire de l’enregistrement neuronal et de optogénétique multicanal, permettant de réduire significativement la taille et la consommation énergétique comparativement aux alternatives commerciales. Ceci est une contribution importante, car c’est la première puce à être doté de ces deux fonctionnalités. Le SoC possède 10 canaux d’enregistrement et 4 canaux de stimulation optogénétique. La conception du bioamplificateur inclut une bande passante programmable (0.5 Hz - 7 kHz) et un faible bruit referré à l’entré (IRN de 3.2 μVrms), ce qui permet de cibler différents types de signaux biologiques (PA, LFP, etc.). Le convertisseur analogique numérique (ADC) de type Delta- Sigma (DS) MASH 1-1-1 est conçu pour fonctionner de faibles taux de sur-échantillonnage (OSR _50) pour réduire sa consommation et possède une résolution programmable (ENOB de 9.75 Bits avec un OSR de 25). Cet ADC exploite une nouvelle technique réduisant la taille du circuit en soustrayant la sortie de chaque branche du DS dans le domaine numérique, comparativement à la méthode analogique classique. La consommation totale d’un canal d’enregistrement est de 11.2 μW. Le SoC implémente un nouveau circuit de stimulation optique basé sur une source de courant de type cascode avec rétroaction, ce qui permet d’accommoder une large gamme de LED et de tensions de batterie comparativement aux circuits existants. Le SoC est intégré dans un système optogénétique sans fil et validé in vivo. À ce jour et en excluant ce projet, aucun système sans-fil ne fait de l’optogénétique en boucle fermée simultanément au suivi temps réel de l’activité neuronale. Une contribution importante de ce travail est d’avoir développé le premier système optogénétique multicanal qui est capable de fonctionner en boucle fermée et le premier à être validé lors d’expériences in vivo impliquant des animaux libres de leurs mouvements. Pour ce faire, la troisième phase du projet a visé la conception d’un SoC CMOS numérique, appelé neural decoder integrated circuit (ND-IC). Le ND-IC et le SoC développé lors de la phase 2 ont été intégrés dans un système optogénétique sans fil. Le ND-IC possède 3 modules : 1) le détecteur de PA adaptatif, 2) le module de compression possédant un nouvel arbre de tri pour discriminer les coefficients, et 3) le module de classement automatique des PA qui réutilise les données générées par le module de détection et de compression pour réduire sa complexité. Un lien entre un canal d’enregistrement et un canal de stimulation est établi selon l’association de chaque PA à un neurone, grâce à la classification, et selon l’activité de ce neurone dans le temps. Le ND-IC consomme 56.9 μW et occupe 0.08 mm2 par canal. Le système pèse 1.05 g, occupe un volume de 1.12 cm3, possède une autonomie de 3h, et est validé in vivo.The future of brain research lies in the development of new technologies that will help understand how this complex organ processes, integrates and transfers information. Among these, optogenetics is a recent technology that allows the use of light to selectively activate neurons in the cortex of transgenic animals to observe their effect in a large biological network. This experimental setting is typically based on observing the neuronal activity of transgenic mice, as they express a wide variety of genes and diseases, while being inexpensive. However, most available neural recording or optogenetic devices are not suitable, because they are hard-wired, too heavy and/or too simplistic. Unfortunately, few wireless systems exist, and they are greatly limited by the required bandwidth to transmit neural data, while not providing simultaneous multi-channel neural recording and optogenetic, a must for stimulating and observing several areas of the brain. In current devices, the analysis of the neuronal data is performed ex situ, while the research would greatly benefit from wireless systems that are smart enough to interpret and stimulate the neurons in closed-loop, in situ. The goal of this project is to design analog-digital circuits for acquisition and processing of neural signals, algorithms for analysis and processing of these signals and miniature electrooptical wireless systems for: i) Conducting experiments combining high-resolution multi-channel neuronal recording and high-resolution multi-channel optogenetics with freely-moving animals. ii) Conduct optogenetic experiments synchronized with the neural recording, i.e. in closed loop, with freely-moving animals. iii) Increase the resolution while reducing the size, weight and energy consumption of the wireless optogenetic systems to minimize the impact of research with small animals. This project is in 3 phases, and its main contributions have been reported in ten conferences (ISSCC, ISCAS, EMBC, etc.) and four published journal papers, or submitted, as well as in a patent and two disclosures. The design of a high resolution optogenetic system poses several challenges. In particular, since the neuronal signals have a high frequency content (10 kHz), the number of chanv nels under observation is limited by the bandwidth of the wireless transmitters (2-4 channels in general). Thus, the first phase of the project focused on the development of neural signal compression algorithms and their integration into a high-resolution miniature and lightweight wireless optogenetics system (2.8g), having 32 recording channels and 32 optical stimulation channels. This system detects, compresses and transmits the waveforms of the signals produced by the neurons, i.e. action potentials (AP), in real time, via an embedded low-power field programmable gate array (FPGA). This processor implements an AP detector algorithm based on adaptive thresholding, which allows to compress the signals by transmitting only the detected waveforms. Each AP is further compressed by a Symmlet-2 discrete wavelet transform (DWT) followed dynamic discrimination and requantification of the DWT coefficients, making it possible to achieve high compression ratios with a good reconstruction quality. Results demonstrate that this algorithm is more robust than existing approach, while allowing to reconstruct the compressed signals with better quality (average SNDR of 25 dB 5% for a compression ratio (CR) of 4.2). With detection, CRs greater than 500 are reported during the in vivo validation. The use of commercial components in wireless optogenetic systems increases the size and power consumption, while not being optimized for this application. The second phase of the project consisted in designing a complementary metal oxide semiconductor (CMOS) system-on-chip (SoC) for neural recording and multi-channel optogenetics, which significantly reduces the size and energy consumption compared to commercial alternatives. This is important contribution, since it’s the first chip to integrate both features. This SoC has 10 recording channels and 4 optogenetic stimulation channels. The bioamplifier design includes a programmable bandwidth (0.5 Hz -7 kHz) and a low input-referred noise (IRN of 3.2 μVrms), which allows targeting different biological signals (AP, LFP, etc.). The Delta-Sigma (DS) MASH 1-1-1 low-power analog-to-digital converter (ADC) is designed to work with low OSR (50), as to reduce its power consumption, and has a programmable resolution (ENOB of 9.75 bits with an OSR of 25). This ADC uses a new technique to reduce its circuit size by subtracting the output of each DS branch in the digital domain, rather than in the analog domain, as done conventionally. A recording channel, including the bioamplifier, the DS and the decimation filter, consumes 11.2 μW. Optical stimulation is performed with an on-chip LED driver using a regulated cascode current source with feedback, which accommodates a wide range of LED parameters and battery voltages. The SoC is integrated into a wireless optogenetic platform and validated in vivo.To date and excluding this project, no wireless system is making closed-loop optogenetics simultaneously to real-time monitoring of neuronal activity. An important contribution of this work is to have developed the first multi-channel optogenetic system that is able to work in closed-loop, and the first to be validated during in vivo experiments involving freely-moving animals. To do so, the third phase of the project aimed to design a digital CMOS chip, called neural decoder integrated circuit (ND-IC). The ND-IC and the SoC developed in Phase 2 are integrated within a wireless optogenetic system. The ND-IC has 3 main cores: 1) the adaptive AP detector core, 2) the compression core with a new sorting tree for discriminating the DWT coefficients, and 3 ) the AP automatic classification core that reuses the data generated by the detection and compression cores to reduce its complexity. A link between a recording channel and a stimulation channel is established according to the association of each AP with a neuron, thanks to the classification, and according to the bursting activity of this neuron. The ND-IC consumes 56.9 μW and occupies 0.08 mm2 per channel. The system weighs 1.05 g, occupies a volume of 1.12 cm3, has an autonomy of 3h, and is validated in vivo